[PATCH] irqchip/irq-brcmstb-l2: add write memory barrier before exit

[PATCH] irqchip/irq-brcmstb-l2: add write memory barrier before exit

[Doug Berger]

It was observed on Broadcom devices that use GIC v3 architecture
L1 interrupt controllers as the parent of brcmstb-l2 interrupt
controllers that the deactivation of the parent irq could happen
before the brcmstb-l2 deasserted its output. This would lead the
GIC to reactivate the irq only to find that no L2 interrupt was
pending. The result was a spurious interrupt invoking the
handle_bad_irq() with its associated messaging. While this did
not create a functional problem it is a waste of cycles.

The hazard exists because the memory mapped bus writes to the
brcmstb-l2 registers are buffered and the GIC v3 architecture
uses a very efficient system register write to deactivate the
interrupt. This commit adds a write memory barrier prior to
invoking chained_irq_exit() to introduce a dsb(st) on those
systems to ensure the system register write cannot be executed
until the memory mapped writes are visible to the system.

Signed-off-by: Doug Berger <opendmb@gmail.com>
---
 drivers/irqchip/irq-brcmstb-l2.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 5559c943f03f..63aed60dd3f1 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -2,7 +2,7 @@
 /*
  * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
  *
- * Copyright (C) 2014-2017 Broadcom
+ * Copyright (C) 2014-2023 Broadcom
  */
 
 #define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
@@ -112,6 +112,9 @@ static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
 		generic_handle_domain_irq(b->domain, irq);
 	} while (status);
 out:
+	/* Don't ack parent before all device writes are done */
+	wmb();
+
 	chained_irq_exit(chip, desc);
 }
 
-- 
2.34.1


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Re: [PATCH] irqchip/irq-brcmstb-l2: add write memory barrier before exit

[Florian Fainelli]

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On 12/20/2023 8:32 PM, Doug Berger wrote:
> It was observed on Broadcom devices that use GIC v3 architecture
> L1 interrupt controllers as the parent of brcmstb-l2 interrupt
> controllers that the deactivation of the parent irq could happen
> before the brcmstb-l2 deasserted its output. This would lead the
> GIC to reactivate the irq only to find that no L2 interrupt was
> pending. The result was a spurious interrupt invoking the
> handle_bad_irq() with its associated messaging. While this did
> not create a functional problem it is a waste of cycles.
> 
> The hazard exists because the memory mapped bus writes to the
> brcmstb-l2 registers are buffered and the GIC v3 architecture
> uses a very efficient system register write to deactivate the
> interrupt. This commit adds a write memory barrier prior to
> invoking chained_irq_exit() to introduce a dsb(st) on those
> systems to ensure the system register write cannot be executed
> until the memory mapped writes are visible to the system.
> 
> Signed-off-by: Doug Berger <opendmb@gmail.com>

Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>

I would be even keen on slapping a:

Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box 
Level-2 interrupt controller")

Thanks Doug!
-- 
Florian

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Re: [PATCH] irqchip/irq-brcmstb-l2: add write memory barrier before exit

[Florian Fainelli]

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On 12/21/23 03:14, Florian Fainelli wrote:
> 
> 
> On 12/20/2023 8:32 PM, Doug Berger wrote:
>> It was observed on Broadcom devices that use GIC v3 architecture
>> L1 interrupt controllers as the parent of brcmstb-l2 interrupt
>> controllers that the deactivation of the parent irq could happen
>> before the brcmstb-l2 deasserted its output. This would lead the
>> GIC to reactivate the irq only to find that no L2 interrupt was
>> pending. The result was a spurious interrupt invoking the
>> handle_bad_irq() with its associated messaging. While this did
>> not create a functional problem it is a waste of cycles.
>>
>> The hazard exists because the memory mapped bus writes to the
>> brcmstb-l2 registers are buffered and the GIC v3 architecture
>> uses a very efficient system register write to deactivate the
>> interrupt. This commit adds a write memory barrier prior to
>> invoking chained_irq_exit() to introduce a dsb(st) on those
>> systems to ensure the system register write cannot be executed
>> until the memory mapped writes are visible to the system.
>>
>> Signed-off-by: Doug Berger <opendmb@gmail.com>
> 
> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
> 
> I would be even keen on slapping a:
> 
> Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box 
> Level-2 interrupt controller")
> 
> Thanks Doug!

Thomas, are you able to apply Doug's patch including the Fixes tag, or 
do you need it to be re-submitted with that tag as well as my Acked-by?

Thanks!
-- 
Florian


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