[PATCH 3/5] arm: dts: marvell: clearfog-gtr: fix various off-by-1 gpio numbers

[Josua Mayer <josua@solid-run.com>]

Various control signals such as sfp module-absence, pci-e reset or led
gpios had off-by-1 mistakes where calculation from mpp number to gpio
index in bank 1 was incorrect.

Fix all such mistakes, and add explicit pinctrl entries for those gpios
where missing.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 .../dts/marvell/armada-385-clearfog-gtr.dtsi  | 61 ++++++++++++++-----
 1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
index 8eabb60765b0..d43bab0fe884 100644
--- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
+++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
@@ -162,6 +162,22 @@ cf_gtr_isolation_pins: cf-gtr-isolation-pins {
 					marvell,function = "gpio";
 				};
 
+				cf_gtr_led_pins: led-pins {
+					marvell,pins = "mpp42", "mpp52";
+					marvell,function = "gpio";
+				};
+
+				cf_gtr_lte_disable_pins: lte-disable-pins {
+					marvell,pins = "mpp34";
+					marvell,function = "gpio";
+				};
+
+				cf_gtr_pci_pins: pci-pins {
+					// pci reset
+					marvell,pins = "mpp33", "mpp35";
+					marvell,function = "gpio";
+				};
+
 				cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
 					marvell,pins = "mpp48";
 					marvell,function = "gpio";
@@ -179,6 +195,12 @@ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
 					marvell,function = "sd0";
 				};
 
+				cf_gtr_sfp0_pins: sfp0-pins {
+					/* sfp modabs, txdisable */
+					marvell,pins = "mpp25", "mpp46";
+					marvell,function = "gpio";
+				};
+
 				cf_gtr_spi1_cs_pins: spi1-cs-pins {
 					marvell,pins = "mpp59";
 					marvell,function = "spi1";
@@ -193,6 +215,11 @@ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
 					marvell,pins = "mpp22";
 					marvell,function = "gpio";
 				};
+
+				cf_gtr_wifi_disable_pins: wifi-disable-pins {
+					marvell,pins = "mpp30", "mpp31";
+					marvell,function = "gpio";
+				};
 			};
 
 			sdhci@d8000 {
@@ -221,34 +248,38 @@ usb3@f8000 {
 		};
 
 		pcie {
+			pinctrl-0 = <&cf_gtr_pci_pins>;
+			pinctrl-names = "default";
 			status = "okay";
 			/*
 			 * The PCIe units are accessible through
 			 * the mini-PCIe connectors on the board.
 			 */
 			pcie@1,0 {
-				reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+				reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 				status = "okay";
 			};
 
 			pcie@2,0 {
-				reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+				reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 				status = "okay";
 			};
 
 			pcie@3,0 {
-				reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+				reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
 				status = "okay";
 			};
 		};
 	};
 
+	/* CON5 */
 	sfp0: sfp {
 		compatible = "sff,sfp";
+		pinctrl-0 = <&cf_gtr_sfp0_pins>;
+		pinctrl-names = "default";
 		i2c-bus = <&i2c1>;
-		los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 	};
 
 	gpio-keys {
@@ -258,14 +289,14 @@ gpio-keys {
 
 		button-0 {
 			label = "Rear Button";
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 			linux,can-disable;
 			linux,code = <BTN_0>;
 		};
 
 		button-1 {
 			label = "Front Button";
-			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
 			linux,can-disable;
 			linux,code = <BTN_1>;
 		};
@@ -273,17 +304,19 @@ button-1 {
 
 	gpio-leds {
 		compatible = "gpio-leds";
+		pinctrl-0 = <&cf_gtr_led_pins>;
+		pinctrl-names = "default";
 
 		led1 {
 			function = LED_FUNCTION_CPU;
 			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 		};
 
 		led2 {
 			function = LED_FUNCTION_HEARTBEAT;
 			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 		};
 	};
 };
@@ -408,7 +441,7 @@ &ahci1 {
 };
 
 &gpio0 {
-	pinctrl-0 = <&cf_gtr_fan_pwm>;
+	pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
 	pinctrl-names = "default";
 
 	wifi-disable {
@@ -420,12 +453,12 @@ wifi-disable {
 };
 
 &gpio1 {
-	pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
+	pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
 	pinctrl-names = "default";
 
 	lte-disable {
 		gpio-hog;
-		gpios = <2 GPIO_ACTIVE_LOW>;
+		gpios = <3 GPIO_ACTIVE_LOW>;
 		output-low;
 		line-name = "lte-disable";
 	};
@@ -436,14 +469,14 @@ lte-disable {
 	 */
 	sar-isolation {
 		gpio-hog;
-		gpios = <15 GPIO_ACTIVE_LOW>;
+		gpios = <16 GPIO_ACTIVE_LOW>;
 		output-low;
 		line-name = "sar-isolation";
 	};
 
 	poe-reset {
 		gpio-hog;
-		gpios = <16 GPIO_ACTIVE_LOW>;
+		gpios = <17 GPIO_ACTIVE_LOW>;
 		output-low;
 		line-name = "poe-reset";
 	};
-- 
2.35.3


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