From: kernel test robot <lkp@intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: oe-kbuild-all@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, arm@kernel.org,
Arnd Bergmann <arnd@arndb.de>
Subject: [soc:soc/arm 5/5] arch/arm/kernel/perf_event_v6.c:144:23: warning: unused variable 'armv6mpcore_perf_map'
Date: Mon, 25 Dec 2023 05:23:48 +0800 [thread overview]
Message-ID: <202312250521.K3pNHbty-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git soc/arm
head: 2560cffd2134c2e070dee369b37f6e55438087f9
commit: 2560cffd2134c2e070dee369b37f6e55438087f9 [5/5] ARM: Delete ARM11MPCore (ARM11 ARMv6K SMP) support
config: arm-randconfig-r111-20231224 (https://download.01.org/0day-ci/archive/20231225/202312250521.K3pNHbty-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce: (https://download.01.org/0day-ci/archive/20231225/202312250521.K3pNHbty-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312250521.K3pNHbty-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> arch/arm/kernel/perf_event_v6.c:144:23: warning: unused variable 'armv6mpcore_perf_map' [-Wunused-const-variable]
static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
^
>> arch/arm/kernel/perf_event_v6.c:154:23: warning: unused variable 'armv6mpcore_perf_cache_map' [-Wunused-const-variable]
static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
^
arch/arm/kernel/perf_event_v6.c:455:13: warning: unused function 'armv6mpcore_pmu_disable_event' [-Wunused-function]
static void armv6mpcore_pmu_disable_event(struct perf_event *event)
^
3 warnings generated.
vim +/armv6mpcore_perf_map +144 arch/arm/kernel/perf_event_v6.c
43eab87828fee6 Will Deacon 2010-11-13 138
43eab87828fee6 Will Deacon 2010-11-13 139 /*
43eab87828fee6 Will Deacon 2010-11-13 140 * The hardware events that we support. We do support cache operations but
43eab87828fee6 Will Deacon 2010-11-13 141 * we have harvard caches and no way to combine instruction and data
43eab87828fee6 Will Deacon 2010-11-13 142 * accesses/misses in hardware.
43eab87828fee6 Will Deacon 2010-11-13 143 */
43eab87828fee6 Will Deacon 2010-11-13 @144 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
cf20ae8cfcb3ab Mark Rutland 2014-05-30 145 PERF_MAP_ALL_UNSUPPORTED,
43eab87828fee6 Will Deacon 2010-11-13 146 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
43eab87828fee6 Will Deacon 2010-11-13 147 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
43eab87828fee6 Will Deacon 2010-11-13 148 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
43eab87828fee6 Will Deacon 2010-11-13 149 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
0445e7a58e794d Will Deacon 2011-09-29 150 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
0445e7a58e794d Will Deacon 2011-09-29 151 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
43eab87828fee6 Will Deacon 2010-11-13 152 };
43eab87828fee6 Will Deacon 2010-11-13 153
43eab87828fee6 Will Deacon 2010-11-13 @154 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
43eab87828fee6 Will Deacon 2010-11-13 155 [PERF_COUNT_HW_CACHE_OP_MAX]
43eab87828fee6 Will Deacon 2010-11-13 156 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
cf20ae8cfcb3ab Mark Rutland 2014-05-30 157 PERF_CACHE_MAP_ALL_UNSUPPORTED,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 158
cf20ae8cfcb3ab Mark Rutland 2014-05-30 159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 160 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 161 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 162 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 163
cf20ae8cfcb3ab Mark Rutland 2014-05-30 164 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 165
43eab87828fee6 Will Deacon 2010-11-13 166 /*
cf20ae8cfcb3ab Mark Rutland 2014-05-30 167 * The ARM performance counters can count micro DTLB misses, micro ITLB
cf20ae8cfcb3ab Mark Rutland 2014-05-30 168 * misses and main TLB misses. There isn't an event for TLB misses, so
cf20ae8cfcb3ab Mark Rutland 2014-05-30 169 * use the micro misses here and if users want the main TLB misses they
cf20ae8cfcb3ab Mark Rutland 2014-05-30 170 * can use a raw counter.
43eab87828fee6 Will Deacon 2010-11-13 171 */
cf20ae8cfcb3ab Mark Rutland 2014-05-30 172 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 173 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 174
cf20ae8cfcb3ab Mark Rutland 2014-05-30 175 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
cf20ae8cfcb3ab Mark Rutland 2014-05-30 176 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
43eab87828fee6 Will Deacon 2010-11-13 177 };
43eab87828fee6 Will Deacon 2010-11-13 178
:::::: The code at line 144 was first introduced by commit
:::::: 43eab87828fee65f89f4088736b2b7a187390a2f ARM: perf: separate PMU backends into multiple files
:::::: TO: Will Deacon <will.deacon@arm.com>
:::::: CC: Will Deacon <will.deacon@arm.com>
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