From mboxrd@z Thu Jan  1 00:00:00 1970
From: LW@KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Mon, 9 Jan 2012 08:17:17 +0100
Subject: mxs: enable phy-clock in the driver?
In-Reply-To: <20120109072121.GN1835@S2101-09.ap.freescale.net>
References: <20120108144558.GB2544@pengutronix.de>
 <20120109013404.GD1835@S2101-09.ap.freescale.net>
 <20234.35823.411762.856482@ipc1.ka-ro>
 <20120109065845.GL1835@S2101-09.ap.freescale.net>
 <20234.37290.114047.36369@ipc1.ka-ro>
 <20120109072121.GN1835@S2101-09.ap.freescale.net>
Message-ID: <20234.38013.186263.46846@ipc1.ka-ro>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi,

Shawn Guo writes:
> On Mon, Jan 09, 2012 at 08:05:14AM +0100, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Shawn Guo writes:
> > > On Mon, Jan 09, 2012 at 07:40:47AM +0100, Lothar Wa?mann wrote:
> > > > The TX28 derives its PHY clock from the ENET_CLK pin of the
> > > > processor. Thus the CLK_ENET_TIME should be enabled by the driver as
> > > > mentioned in <20120108033238.GA19721@S2101-09.ap.freescale.net>
> > > > 
> > > Can you give a web link for that message?
> > > 
> > It's your own email from "Sun, 8 Jan 2012 11:32:40 +0800" with the
> > subject "Re: MX28 fec clock frequency":
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/079556.html
> > 
> Ah, yes.  But what I said there is the CLK_ENET_TIME should be enabled
> by PTP support, not the need of clocking external phy required by
> particular board design.
> 
My point was, that it is the same clock. Thus, not "pll2" but
"enet_ptp" or whatever it's name will be needs to be enabled for the
Ethernet PHY on TX28.


Lothar Wa?mann
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