[PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

[PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

[Siddharth Vadapalli]

TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
The controller on J722S SoC is similar to the one present on TI's AM64
SoC, with the difference being that the controller on AM64 SoC supports
up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.

Update the bindings with a new compatible for J722S SoC.

Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

Hello,

This patch is based on linux-next tagged next-20240122.

v1:
https://lore.kernel.org/r/20240117102526.557006-1-s-vadapalli@ti.com/
Changes since v1:
- Dropped patches 1/3 and 2/3 of the v1 series as discussed in the v1
  thread.
- Updated patch 3/3 which is the v1 for this patch by dropping the checks
  for the "num-lanes" property and "max-link-speed" property since the PCI
  driver already validates the "num-lanes" property.

Regards,
Siddharth.

 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index b7a534cef24d..a7b5c4ce2744 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -14,6 +14,7 @@ properties:
   compatible:
     oneOf:
       - const: ti,j721e-pcie-host
+      - const: ti,j722s-pcie-host
       - const: ti,j784s4-pcie-host
       - description: PCIe controller in AM64
         items:
-- 
2.34.1


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Re: [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

[Conor Dooley]

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On Mon, Jan 22, 2024 at 12:14:57PM +0530, Siddharth Vadapalli wrote:
> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
> The controller on J722S SoC is similar to the one present on TI's AM64
> SoC, with the difference being that the controller on AM64 SoC supports
> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
> 
> Update the bindings with a new compatible for J722S SoC.

Since the difference is just that this device supports a higher link
speed, should it not have a fallback compatible to the am64 variant?
Or is the programming model different for this device for the lower link
speeds different?

Thanks,
Conor.

> 
> Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> 
> Hello,
> 
> This patch is based on linux-next tagged next-20240122.
> 
> v1:
> https://lore.kernel.org/r/20240117102526.557006-1-s-vadapalli@ti.com/
> Changes since v1:
> - Dropped patches 1/3 and 2/3 of the v1 series as discussed in the v1
>   thread.
> - Updated patch 3/3 which is the v1 for this patch by dropping the checks
>   for the "num-lanes" property and "max-link-speed" property since the PCI
>   driver already validates the "num-lanes" property.
> 
> Regards,
> Siddharth.
> 
>  Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index b7a534cef24d..a7b5c4ce2744 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -14,6 +14,7 @@ properties:
>    compatible:
>      oneOf:
>        - const: ti,j721e-pcie-host
> +      - const: ti,j722s-pcie-host
>        - const: ti,j784s4-pcie-host
>        - description: PCIe controller in AM64
>          items:
> -- 
> 2.34.1
> 

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Re: [PATCH v2] dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC

[Siddharth Vadapalli]

Hello Conor,

On 22/01/24 15:17, Conor Dooley wrote:
> On Mon, Jan 22, 2024 at 12:14:57PM +0530, Siddharth Vadapalli wrote:
>> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
>> The controller on J722S SoC is similar to the one present on TI's AM64
>> SoC, with the difference being that the controller on AM64 SoC supports
>> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
>>
>> Update the bindings with a new compatible for J722S SoC.
> 
> Since the difference is just that this device supports a higher link
> speed, should it not have a fallback compatible to the am64 variant?
> Or is the programming model different for this device for the lower link
> speeds different?

Thank you for reviewing the patch. I shall add the same fallback compatible that
am64 has which is "ti,j721e-pcie-host". I will post the v3 patch with this
change if that's acceptable.

-- 
Regards,
Siddharth.

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