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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	James Morse <james.morse@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v4 08/10] KVM: arm64: Expose ID_AA64MMFR4_EL1 to guests
Date: Mon, 22 Jan 2024 18:13:42 +0000	[thread overview]
Message-ID: <20240122181344.258974-9-maz@kernel.org> (raw)
In-Reply-To: <20240122181344.258974-1-maz@kernel.org>

We can now expose ID_AA64MMFR4_EL1 to guests, and let NV guests
understand that they cannot really switch HCR_EL2.E2H to 0 on
some platforms.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/nested.c   | 7 +++++++
 arch/arm64/kvm/sys_regs.c | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index ba95d044bc98..d55e809e26cb 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -133,6 +133,13 @@ static u64 limit_nv_id_reg(u32 id, u64 val)
 		val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001);
 		break;
 
+	case SYS_ID_AA64MMFR4_EL1:
+		val = 0;
+		if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
+			val |= FIELD_PREP(NV_FTR(MMFR4, E2H0),
+					  ID_AA64MMFR4_EL1_E2H0_NI_NV1);
+		break;
+
 	case SYS_ID_AA64DFR0_EL1:
 		/* Only limited support for PMU, Debug, BPs and WPs */
 		val &= (NV_FTR(DFR0, PMUVer)	|
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 88b8fbeafaa0..08a9571fa809 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2350,7 +2350,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 					ID_AA64MMFR2_EL1_NV |
 					ID_AA64MMFR2_EL1_CCIDX)),
 	ID_SANITISED(ID_AA64MMFR3_EL1),
-	ID_UNALLOCATED(7,4),
+	ID_SANITISED(ID_AA64MMFR4_EL1),
 	ID_UNALLOCATED(7,5),
 	ID_UNALLOCATED(7,6),
 	ID_UNALLOCATED(7,7),
-- 
2.39.2


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  parent reply	other threads:[~2024-01-22 18:14 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-22 18:13 [PATCH v4 00/10] arm64: Add support for FEAT_E2H0, or lack thereof Marc Zyngier
2024-01-22 18:13 ` [PATCH v4 01/10] arm64: Add macro to compose a sysreg field value Marc Zyngier
2024-02-08 11:40   ` Catalin Marinas
2024-01-22 18:13 ` [PATCH v4 02/10] arm64: cpufeatures: Correctly handle signed values Marc Zyngier
2024-02-08 12:13   ` Catalin Marinas
2024-01-22 18:13 ` [PATCH v4 03/10] arm64: cpufeature: Correctly display signed override values Marc Zyngier
2024-02-08 12:14   ` Catalin Marinas
2024-01-22 18:13 ` [PATCH v4 04/10] arm64: sysreg: Add layout for ID_AA64MMFR4_EL1 Marc Zyngier
2024-02-08 12:25   ` Catalin Marinas
2024-02-08 13:06   ` Miguel Luis
2024-02-08 13:15     ` Marc Zyngier
2024-01-22 18:13 ` [PATCH v4 05/10] arm64: cpufeature: Add ID_AA64MMFR4_EL1 handling Marc Zyngier
2024-02-08 12:25   ` Catalin Marinas
2024-01-22 18:13 ` [PATCH v4 06/10] arm64: cpufeature: Detect HCR_EL2.NV1 being RES0 Marc Zyngier
2024-02-08 12:26   ` Catalin Marinas
2024-02-08 12:27   ` Catalin Marinas
2024-02-12 12:48   ` Marek Szyprowski
2024-02-12 14:00     ` Marc Zyngier
2024-02-12 14:21       ` Marek Szyprowski
2024-01-22 18:13 ` [PATCH v4 07/10] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative Marc Zyngier
2024-02-08 12:27   ` Catalin Marinas
2024-01-22 18:13 ` Marc Zyngier [this message]
2024-01-22 18:13 ` [PATCH v4 09/10] KVM: arm64: Force guest's HCR_EL2.E2H RES1 when NV1 is not implemented Marc Zyngier
2024-01-22 18:13 ` [PATCH v4 10/10] KVM: arm64: Handle Apple M2 as not having HCR_EL2.NV1 implemented Marc Zyngier
2024-02-08 12:29   ` Catalin Marinas
2024-02-02 19:03 ` [PATCH v4 00/10] arm64: Add support for FEAT_E2H0, or lack thereof Oliver Upton
2024-02-08 12:30   ` Catalin Marinas
2024-02-08 15:24 ` Oliver Upton

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