From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E338C46CD2 for ; Wed, 24 Jan 2024 16:40:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type:Cc: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=A8aaWufePH61i0HxDK6dBM6MZa0jQjzLfk9teqblcz8=; b=piq6v4dE10lcAkd7hGF8jqRWp5 1NI7KhHsFn6CYHDDuyUde5yvfgTLbDgPQqpYeLMzd5KVaUmx3r9i0bD9Rv2MnjSaGitcs37IiHKw0 zZud8Ku+sb2qjH+31ASws56C/BoMN25/ulSdaMY3DkSrh0r+E7f8REmg9m1fFSn8FAn5z89a2huK+ fHLmL7W/Qy495LFI222MBkawujkbJT5tN8vsk1PwLz+8KThEArrx2FhSbUx2gC0gl5PTO2+Kyl6Vt C8AaNoS9bx71aT52SIH27yDpxSdwQKZoFRr9NdemEqIRLnzLms1E/4It4OjHlRPmhgQS6HC4tFR1/ 2sxG4tMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rSgHk-004EwF-1d; Wed, 24 Jan 2024 16:39:32 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rSgHg-004EuN-10 for linux-arm-kernel@lists.infradead.org; Wed, 24 Jan 2024 16:39:30 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id DA7AF61D74; Wed, 24 Jan 2024 16:39:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECFABC433F1; Wed, 24 Jan 2024 16:39:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1706114361; bh=0fZCQavj1U8K5GunvCZvb1epaEQ0wifItVZGRlFzcRg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VXNYJeaPQZLz7X9MQ9wSR96fooLL/NCtqDx8tRKMakIvPmgnjQEEyZdTweVs5+lxp qQv7eWa2Fyc2Sw3VhrpukiV7fxxneNWbEN8iLFWWYE4m6DEM3qvKJ0IHh8DGoi3pV8 7Q/B5Ba/fv7zlO0+u3NFXb8wldm0mVKjPYRQUMRKiBer9ks2JWAnP4pNIUNRqBqiSa s5U+76LwRpNnYQX3OixDdRv33l93W4gKBsd36Oj+bDPz9IkWXaiksJYbSWZNIulywF BBUCPurh9LUy3Mx9ayhOcKzobR7VPLMxyeEjdXFDdJamlzrnV746zUuhJpowYAQlb0 vaL5cmybxcDPw== Date: Wed, 24 Jan 2024 16:39:14 +0000 From: Conor Dooley To: Dharma.B@microchip.com Subject: Re: [PATCH v3 3/3] dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format Message-ID: <20240124-lend-emerald-1028fe65cc39@spud> References: <20240118092612.117491-1-dharma.b@microchip.com> <20240118092612.117491-4-dharma.b@microchip.com> <20240118-recent-glorified-fd35d72e006e@spud> <20240119-character-mardi-43571d7fe7d5@wendy> <20240122-stark-duress-2f59294dcf27@spud> <4906b7e2-0ddb-4d3c-a48b-e16278f2d649@microchip.com> MIME-Version: 1.0 In-Reply-To: <4906b7e2-0ddb-4d3c-a48b-e16278f2d649@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240124_083928_434027_3C02A60F X-CRM114-Status: GOOD ( 54.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexandre.belloni@bootlin.com, linux-pwm@vger.kernel.org, Linux4Microchip@microchip.com, dri-devel@lists.freedesktop.org, Conor.Dooley@microchip.com, thierry.reding@gmail.com, krzysztof.kozlowski+dt@linaro.org, claudiu.beznea@tuxon.dev, airlied@gmail.com, sam@ravnborg.org, lee@kernel.org, u.kleine-koenig@pengutronix.de, devicetree@vger.kernel.org, conor+dt@kernel.org, tzimmermann@suse.de, maarten.lankhorst@linux.intel.com, mripard@kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, bbrezillon@kernel.org, linux-kernel@vger.kernel.org, daniel@ffwll.ch Content-Type: multipart/mixed; boundary="===============0838535357070924495==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0838535357070924495== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ujchoulqKTbrEzob" Content-Disposition: inline --ujchoulqKTbrEzob Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 24, 2024 at 05:18:26AM +0000, Dharma.B@microchip.com wrote: > Hi Conor & All, >=20 > On 22/01/24 2:46 pm, Conor Dooley wrote: > > On Mon, Jan 22, 2024 at 03:38:41AM +0000,Dharma.B@microchip.com wrote: > >> Hi Conor, > >> On 19/01/24 5:33 pm, Conor Dooley - M52691 wrote: > >>> On Fri, Jan 19, 2024 at 03:32:49AM +0000,Dharma.B@microchip.com wrot= e: > >>>> On 18/01/24 9:10 pm, Conor Dooley wrote: > >>>>> On Thu, Jan 18, 2024 at 02:56:12PM +0530, Dharma Balasubiramani wro= te: > >>>>>> Convert the atmel,hlcdc binding to DT schema format. > >>>>>> > >>>>>> Adjust the clock-names property to clarify that the LCD controller= expects > >>>>>> one of these clocks (either sys_clk or lvds_pll_clk to be present = but not > >>>>>> both) along with the slow_clk and periph_clk. This alignment with = the actual > >>>>>> hardware requirements will enable accurate device tree configurati= on for > >>>>>> systems using the HLCDC IP. > >>>>>> > >>>>>> Signed-off-by: Dharma Balasubiramani > >>>>>> --- > >>>>>> changelog > >>>>>> v2 -> v3 > >>>>>> - Rename hlcdc-display-controller and hlcdc-pwm to generic names. > >>>>>> - Modify the description by removing the unwanted comments and '|'. > >>>>>> - Modify clock-names simpler. > >>>>>> v1 -> v2 > >>>>>> - Remove the explicit copyrights. > >>>>>> - Modify title (not include words like binding/driver). > >>>>>> - Modify description actually describing the hardware and not the = driver. > >>>>>> - Add details of lvds_pll addition in commit message. > >>>>>> - Ref endpoint and not endpoint-base. > >>>>>> - Fix coding style. > >>>>>> ... > >>>>>> .../devicetree/bindings/mfd/atmel,hlcdc.yaml | 97 +++++++++++= ++++++++ > >>>>>> .../devicetree/bindings/mfd/atmel-hlcdc.txt | 56 ----------- > >>>>>> 2 files changed, 97 insertions(+), 56 deletions(-) > >>>>>> create mode 100644 Documentation/devicetree/bindings/mfd/atmel= ,hlcdc.yaml > >>>>>> delete mode 100644 Documentation/devicetree/bindings/mfd/atmel= -hlcdc.txt > >>>>>> > >>>>>> diff --git a/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yam= l b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml > >>>>>> new file mode 100644 > >>>>>> index 000000000000..eccc998ac42c > >>>>>> --- /dev/null > >>>>>> +++ b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml > >>>>>> @@ -0,0 +1,97 @@ > >>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >>>>>> +%YAML 1.2 > >>>>>> +--- > >>>>>> +$id:http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# > >>>>>> +$schema:http://devicetree.org/meta-schemas/core.yaml# > >>>>>> + > >>>>>> +title: Atmel's HLCD Controller > >>>>>> + > >>>>>> +maintainers: > >>>>>> + - Nicolas Ferre > >>>>>> + - Alexandre Belloni > >>>>>> + - Claudiu Beznea > >>>>>> + > >>>>>> +description: > >>>>>> + The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs ex= poses two > >>>>>> + subdevices, a PWM chip and a Display Controller. > >>>>>> + > >>>>>> +properties: > >>>>>> + compatible: > >>>>>> + enum: > >>>>>> + - atmel,at91sam9n12-hlcdc > >>>>>> + - atmel,at91sam9x5-hlcdc > >>>>>> + - atmel,sama5d2-hlcdc > >>>>>> + - atmel,sama5d3-hlcdc > >>>>>> + - atmel,sama5d4-hlcdc > >>>>>> + - microchip,sam9x60-hlcdc > >>>>>> + - microchip,sam9x75-xlcdc > >>>>>> + > >>>>>> + reg: > >>>>>> + maxItems: 1 > >>>>>> + > >>>>>> + interrupts: > >>>>>> + maxItems: 1 > >>>>>> + > >>>>>> + clocks: > >>>>>> + maxItems: 3 > >>>>> Hmm, one thing I probably should have said on the previous version,= but > >>>>> I missed somehow: It would be good to add an items list to the cloc= ks > >>>>> property here to explain what the 3 clocks are/are used for - espec= ially > >>>>> since there is additional complexity being added here to use either= the > >>>>> sys or lvds clocks. > >>>> May I inquire if this approach is likely to be effective? > >>>> > >>>> clocks: > >>>> items: > >>>> - description: peripheral clock > >>>> - description: generic clock or lvds pll clock > >>>> Once the LVDS PLL is enabled, the pixel clock is used a= s the > >>>> clock for LCDC, so its GCLK is no longer needed. > >>>> - description: slow clock > >>>> maxItems: 3 > >>> Hmm that sounds very suspect to me. "Once the lvdspll is enabled the > >>> generic clock is no longer needed" sounds like both clocks can be pro= vided > >>> to the IP on different pins and their provision is not mutually > >>> exclusive, just that the IP will only actually use one at a time. If > >>> that is the case, then this patch is nott correct and the binding sho= uld > >>> allow for 4 clocks, with both the generic clock and the lvds pll being > >>> present in the DT at the same time. > >>> > >>> I vaguely recall internal discussion about this problem some time back > >>> but the details all escape me. > >> Let's delve deeper into the clock configuration for LCDC_PCK. > >> > >> Considering the flexibility of the design, it appears that both clocks, > >> sys_clk (generic clock) and lvds_pll_clk, can indeed be provided to the > >> IP simultaneously. The crucial aspect, however, is that the IP will > >> utilize only one of these clocks at any given time. This aligns with t= he > >> specific requirements of the application, where the choice of clock > >> depends on whether the LVDS interface or MIPI/DSI is in use. > > If both clocks can physically be provided to the IP then both of them > > should be in the dt. The hcldc appears to me to be a part of the SoC and > > the clock routing to the IP is likely fixed. > >=20 > >> To ensure proper configuration of the pixel clock period, we need to > >> distinctly identify which clocks are being utilized. For instance, in > >> the LVDS interface scenario, the lvds_pll_clk is essential, resulting = in > >> LCDC_PCK being set to the source clock. Conversely, in the MIPI/DSI > >> case, the LCDC GCLK is required, leading to LCDC_PCK being defined as > >> source clock/CLKDIV+2. > >> > >> Considering the potential coexistence of sys_clk and lvds_pll_clk in t= he > >> Device Tree (DT), we may need to introduce an additional flag in the D= T. > >> This flag could serve as a clear indicator of whether the LVDS interfa= ce > >> or MIPI/DSI is being employed. As we discussed to drop this flag and > >> just have any one of the clocks I believe that this approach provides a > >> sensible and scalable solution, allowing for a comprehensive > >> representation of the clocking configuration. > > This is probably a question for the folks on the DRM or media side of > > things, but is it not possible to determine based on the endpoint what > > protocol is required? > > I know that on the media side of things there's an endpoint property > > that can be used to specific the bus-type - is there an equivalent > > property for DRM stuff? >=20 > Yes, it can be done. > I will have the lvds pll in the lvds DT node. > I will just convert the existing text binding to yaml without this=20 > additonal lvds pll clock. If the lvds pll is an input to the hlcdc, you need to add it here. =46rom your description earlier it does sound like it is an input to the hlcdc, but now you are claiming that it is not. I don't know your hardware, so I have no idea which of the two is correct, but it sounds like the former. Without digging into how this works my assumption about the hardware here looks like is that the lvds controller is a clock provider, and that the lvds controller's clock is an optional input for the hlcdc. Can you please explain what provides the lvds pll clock and show an example of how you think the devictree would look with "the lvds pll in the lvds dt node"? Thanks, Conor. --ujchoulqKTbrEzob Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZbE9MgAKCRB4tDGHoIJi 0ginAQDiTOcxYcOB4iMLmpd9gCY1MXm8q9z9ZLXEzCR0Mi9zBQD9GyZo+5NvRMAU GyiMoV1ckQa6rAM/ANP7lVTdT0RY7AA= =3FDx -----END PGP SIGNATURE----- --ujchoulqKTbrEzob-- --===============0838535357070924495== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0838535357070924495==--