From: Andrew Davis <afd@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Andrew Davis <afd@ti.com>
Subject: [PATCH 4/4] arm64: dts: ti: k3-am64: Remove PCIe endpoint node
Date: Wed, 24 Jan 2024 12:36:59 -0600 [thread overview]
Message-ID: <20240124183659.149119-4-afd@ti.com> (raw)
In-Reply-To: <20240124183659.149119-1-afd@ti.com>
This node is an example node for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 19 -------------------
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 6 ------
2 files changed, 25 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index e348114f42e01..d5938f966a2dd 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1041,25 +1041,6 @@ pcie0_rc: pcie@f102000 {
status = "disabled";
};
- pcie0_ep: pcie-ep@f102000 {
- compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
- reg = <0x00 0x0f102000 0x00 0x1000>,
- <0x00 0x0f100000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
- max-link-speed = <2>;
- num-lanes = <1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fck";
- max-functions = /bits/ 8 <1>;
- status = "disabled";
- };
-
epwm0: pwm@23000000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 8c5651d2cf5dd..6412c52c8001a 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -705,12 +705,6 @@ &pcie0_rc {
num-lanes = <1>;
};
-&pcie0_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J12 */
--
2.39.2
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next prev parent reply other threads:[~2024-01-24 18:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-24 18:36 [PATCH 1/4] arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level Andrew Davis
2024-01-24 18:36 ` [PATCH 2/4] arm64: dts: ti: k3-j7200: Remove PCIe endpoint node Andrew Davis
2024-01-24 18:36 ` [PATCH 3/4] arm64: dts: ti: k3-am65: Remove PCIe endpoint nodes Andrew Davis
2024-01-24 18:36 ` Andrew Davis [this message]
2024-02-06 4:41 ` [PATCH 1/4] arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level Vignesh Raghavendra
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