From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0575C47DDF for ; Fri, 26 Jan 2024 17:36:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JJtv0iURmicCpyNDDfg8ScfHl3oSuWyYaLFhEqRNkwU=; b=yMbJQROJRUD5x5 C1zFFU2mp26O76koJFe2N/WAnoxySMPQ0yn9PQrCwRZ+oStQfievGtmI93d95GiT28rS+BAphyw9u V8Zfudngsi373X7Xqw6MUAdh3Wl/+c+29cnhmKLpP7ldDgdN++g0qowX+Ow+MDTIYVo65lFXhyy5t cYq3qc5tB9nf9HnrkTyDjE89BlrrQfNLOmHmsh/Q3Q5jgv0IbuOmyJatMUjWCil+WaJoEswM6hsA4 4ezDXGFOnymZuAp2OuI6DOJIF99jspo4JdPBBpmkdcZNwewTAhz/JJ+G2IF9exsySyCswBtku5zJ0 TlvsG1reJ/sDq5WSLGDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rTQ8F-00000004vOV-3AzA; Fri, 26 Jan 2024 17:36:47 +0000 Received: from mgamail.intel.com ([198.175.65.10]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rTQ8D-00000004vNY-0RGu for linux-arm-kernel@lists.infradead.org; Fri, 26 Jan 2024 17:36:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706290605; x=1737826605; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ieTfurtfat+pVfBbfHgnr7Gb/OnUunNsdTZt3fG9fSs=; b=I2dbSX4MEIMI/4rQghJI0smwT1qejtLyE1atY8JD/c6Ti83As6/gviE5 JMInPPpB1a0/Pxp5WCwdbYVkwMpG+AIqakxQzuK19u12JK2Qwy1CifTU6 oiNn2r9Xgem6R14Vls2/3w7DqIgLBoRhqTGM2WV+33THnsIPFtQomfJDa Uru+9qNrAQrhr6tIPgW5EcCtN5aD/GqoCap260dTKgVAKbXPPywtowIBc IGkuGsTtyph28hEb6U51R3KvPUWxuNrT0EOvYPU+DijbEefJgBw7/LT0m M0Wlh466PwO28rbCnZtVcsjFup8pKJ9huhrUo4IjPtMKiggnjUn1MubbM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="15886420" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="15886420" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2024 09:36:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10964"; a="930424527" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="930424527" Received: from ppglcf2090.png.intel.com ([10.126.160.96]) by fmsmga001.fm.intel.com with ESMTP; 26 Jan 2024 09:36:37 -0800 From: rohan.g.thomas@intel.com To: esben@geanix.com Cc: alexandre.torgue@foss.st.com, conor+dt@kernel.org, davem@davemloft.net, devicetree@vger.kernel.org, edumazet@google.com, fancer.lancer@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, pabeni@redhat.com, peppe.cavallaro@st.com, robh@kernel.org, rohan.g.thomas@intel.com Subject: RE: [PATCH net-next 1/2] dt-bindings: net: snps,dwmac: Time Based Scheduling Date: Sat, 27 Jan 2024 01:36:34 +0800 Message-Id: <20240126173634.13162-1-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <87msss4gtj.fsf@geanix.com> References: <87msss4gtj.fsf@geanix.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240126_093645_285838_995185E0 X-CRM114-Status: GOOD ( 26.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rohan G Thomas On Fri, 26 Jan 2024 09:52:40 +0100, Esben Haabendal wrote: Hi Esben, Thanks for your comments. Like to get some clarification on a few things. > >> > >>Seems like OS configuration and policy. > > > > Tx queues need to be configured for TBS during hw setup itself as > > special enhanced descriptors are used by the hw for TBS support > > enabled queues. Switching between enhanced and normal descriptors on > > run is not feasible. So this flag is for enabling "Enhanced > > Descriptors for Time Based Scheduling". This I think is a hw specific > > requirement. > > Support for enhanced descriptors is definitely hardware specific. > Enabling the use of enhanced descriptors is a configuration choice. > > The tricky part here is that the whole devicetree bindings story for the > stmmac driver is filled with such configuration choices. As such, it is > only natural to add the property you are suggesting here. I completely > agree. But you can also argue that it is "wrong", because it does not > just describe the hardware, but also a configuration choice. Isn't this requirement of using enhanced tx desc instead of normal tx desc to support TBS is specific to Synopsys IP? Switching from normal desc to enhanced desc at the time of tc-etf qdisc offload cannot be done without traffic disruption, which I don't think is acceptable. Since this behavior is IP specific, can we consider this as an OS configuration choice? Agreed that this feature(use of enhanced desc) can be enabled from glue drivers. But I added this dt property, thinking this feature is specific and common to DWMAC core and we can enable this feature for stmmac platform driver without a glue driver. If this is not acceptable, I can think of doing this from the glue driver. > >>Doesn't eh DWMAC have capability registers for supported features? Or > >>did they forget per queue capabilities? > > > > Yes, capability registers are available. For DWMAC5 IP, if TBSSEL bit > > is set, then TBS is supported by all Tx queues. > > Not true. Some NXP imx8 and imx9 chips support Synopsys MAC 5.10a IP, > and does not support TBS for queue 0. And they have TBSSEL bit set, but > no TBS_CH support. AFAIU from Synopsys DWMAC5 Databook, all queues support TBS. But TBS cannot coexist with TSO. So all glue drivers enabling TBS feature avoid queue 0 to support TSO. Please correct me if I'm wrong. > > > For DWXGMAC IP, if TBSSEL bit is set, then TBS is supported by TBS_CH > > number of Tx queues starting from the highest Tx queue. But because of > > the hw limitations mentioned above, TBS cannot be enabled for all > > capable queues. > > BR, Rohan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel