Re: [PATCH v8 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support

[kernel test robot <lkp@intel.com>]

Hi Aleksandr,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on sunxi/sunxi/for-next linus/master v6.8-rc2 next-20240202]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Aleksandr-Shubin/dt-bindings-pwm-Add-binding-for-Allwinner-D1-T113-S3-R329-PWM-controller/20240131-210313
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20240131125920.2879433-3-privatesub2%40gmail.com
patch subject: [PATCH v8 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240203/202402032222.BiIrD3g4-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240203/202402032222.BiIrD3g4-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202402032222.BiIrD3g4-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pwm/pwm-sun20i.c:47: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * SUN20I_PWM_MAGIC is used to quickly compute the values of the clock dividers


vim +47 drivers/pwm/pwm-sun20i.c

    45	
    46	/**
  > 47	 * SUN20I_PWM_MAGIC is used to quickly compute the values of the clock dividers
    48	 * div_m (SUN20I_PWM_CLK_CFG_DIV_M) & prescale_k (SUN20I_PWM_CTL_PRESCAL_K)
    49	 * without using a loop. These dividers limit the # of cycles in a period
    50	 * to SUN20I_PWM_PCNTR_SIZE by applying a scaling factor of
    51	 * 1/(div_m * (prescale_k + 1)) to the clock source.
    52	 *
    53	 * SUN20I_PWM_MAGIC is derived by solving for div_m and prescale_k
    54	 * such that for a given requested period,
    55	 *
    56	 * i) div_m is minimized for any prescale_k ≤ SUN20I_PWM_CTL_PRESCAL_K_MAX,
    57	 * ii) prescale_k is minimized.
    58	 *
    59	 * The derivation proceeds as follows, with val = # of cycles for reqested
    60	 * period:
    61	 *
    62	 * for a given value of div_m we want the smallest prescale_k such that
    63	 *
    64	 * (val >> div_m) // (prescale_k + 1) ≤ 65536 (SUN20I_PWM_PCNTR_SIZE)
    65	 *
    66	 * This is equivalent to:
    67	 *
    68	 * (val >> div_m) ≤ 65536 * (prescale_k + 1) + prescale_k
    69	 * ⟺ (val >> div_m) ≤ 65537 * prescale_k + 65536
    70	 * ⟺ (val >> div_m) - 65536 ≤ 65537 * prescale_k
    71	 * ⟺ ((val >> div_m) - 65536) / 65537 ≤ prescale_k
    72	 *
    73	 * As prescale_k is integer, this becomes
    74	 *
    75	 * ((val >> div_m) - 65536) // 65537 ≤ prescale_k
    76	 *
    77	 * And is minimized at
    78	 *
    79	 * ((val >> div_m) - 65536) // 65537
    80	 *
    81	 * Now we pick the smallest div_m that satifies prescale_k ≤ 255
    82	 * (i.e SUN20I_PWM_CTL_PRESCAL_K_MAX),
    83	 *
    84	 * ((val >> div_m) - 65536) // 65537 ≤ 255
    85	 * ⟺ (val >> div_m) - 65536 ≤ 255 * 65537 + 65536
    86	 * ⟺ val >> div_m ≤ 255 * 65537 + 2 * 65536
    87	 * ⟺ val >> div_m < (255 * 65537 + 2 * 65536 + 1)
    88	 * ⟺ div_m = fls((val) / (255 * 65537 + 2 * 65536 + 1))
    89	 *
    90	 * Suggested by Uwe Kleine-König
    91	 */
    92	#define SUN20I_PWM_MAGIC			(255 * 65537 + 2 * 65536 + 1)
    93	

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