[PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

[PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

[Anand Moon]

As per S905 and S905X datasheet add missing cache information to
the Amlogic GXBB and GXL SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Datasheet
[0] https://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 2673f0dbafe7..e141ade5e49b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -95,6 +95,12 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
 			#cooling-cells = <2>;
@@ -105,6 +111,12 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
 			#cooling-cells = <2>;
@@ -115,6 +127,12 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
 			#cooling-cells = <2>;
@@ -125,6 +143,12 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			clocks = <&scpi_dvfs 0>;
 			#cooling-cells = <2>;
@@ -134,6 +158,9 @@ l2: l2-cache0 {
 			compatible = "cache";
 			cache-level = <2>;
 			cache-unified;
+			cache-size = <0x7d000>; /* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 
-- 
2.43.0


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Re: [PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

[Anand Moon]

Hi Neil,

On Mon, 5 Feb 2024 at 22:50, Anand Moon <linux.amoon@gmail.com> wrote:
>
> As per S905 and S905X datasheet add missing cache information to
> the Amlogic GXBB and GXL SoC.
>
> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
>         32KB of L1 data cache available.
> - Along with 512KB Unified L2 cache.
>
> To improve system performance.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Datasheet
> [0] https://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
> ---

As per the Arm Cortex A53 TRM documentation
[0] https://developer.arm.com/documentation/ddi0500/j/Introduction/Implementation-options?lang=en

Since this SoC supports arm-pmu we could  read cache info using perf
[1] https://www.baeldung.com/linux/analyze-cache-misses

[alarm@archl-librecm ~]$ sudo perf list

List of pre-defined events (to be used in -e or -M):

  branch-instructions OR branches                    [Hardware event]
  branch-misses                                      [Hardware event]
  bus-cycles                                         [Hardware event]
  cache-misses                                       [Hardware event]
  cache-references                                   [Hardware event]
  cpu-cycles OR cycles                               [Hardware event]
  instructions                                       [Hardware event]
  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  cgroup-switches                                    [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]

armv8_cortex_a53:
  L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/
  L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/
  L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/
  L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/
  L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/
  dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/
  iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/
  branch-loads OR armv8_cortex_a53/branch-loads/
  branch-load-misses OR armv8_cortex_a53/branch-load-misses/
  node-loads OR armv8_cortex_a53/node-loads/
  node-stores OR armv8_cortex_a53/node-stores/
  br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event]
  br_mis_pred OR armv8_cortex_a53/br_mis_pred/       [Kernel PMU event]
  br_pred OR armv8_cortex_a53/br_pred/               [Kernel PMU event]
  bus_access OR armv8_cortex_a53/bus_access/         [Kernel PMU event]
  bus_cycles OR armv8_cortex_a53/bus_cycles/         [Kernel PMU event]
  cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event]
  cpu_cycles OR armv8_cortex_a53/cpu_cycles/         [Kernel PMU event]
  exc_return OR armv8_cortex_a53/exc_return/         [Kernel PMU event]

[alarm@archl-librecm ~]$ perf stat -B -e
cache-references,cache-misses,cycles,instructions,branches,faults,migrations
sleep 5

 Performance counter stats for 'sleep 5':

             52794      cache-references:u
              2311      cache-misses:u                   #    4.38% of
all cache refs
            480343      cycles:u
            140018      instructions:u                   #    0.29
insn per cycle
             15012      branches:u
                46      faults:u
                 0      migrations:u

       5.008073381 seconds time elapsed

       0.000000000 seconds user
       0.006952000 seconds sys

Thanks



-Anand

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Re: [PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

[Anand Moon]

Hi Neil,

On Tue, 27 Feb 2024 at 18:33, Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Neil,
>
> On Mon, 5 Feb 2024 at 22:50, Anand Moon <linux.amoon@gmail.com> wrote:
> >
> > As per S905 and S905X datasheet add missing cache information to
> > the Amlogic GXBB and GXL SoC.
> >
> > - Each Cortex-A53 core has 32KB of L1 instruction cache available and
> >         32KB of L1 data cache available.
> > - Along with 512KB Unified L2 cache.
> >
> > To improve system performance.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > Datasheet
> > [0] https://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
> > ---
>
> As per the Arm Cortex A53 TRM documentation
> [0] https://developer.arm.com/documentation/ddi0500/j/Introduction/Implementation-options?lang=en
>
> Since this SoC supports arm-pmu we could  read cache info using perf
> [1] https://www.baeldung.com/linux/analyze-cache-misses
>
> [alarm@archl-librecm ~]$ sudo perf list
>
> List of pre-defined events (to be used in -e or -M):
>
>   branch-instructions OR branches                    [Hardware event]
>   branch-misses                                      [Hardware event]
>   bus-cycles                                         [Hardware event]
>   cache-misses                                       [Hardware event]
>   cache-references                                   [Hardware event]
>   cpu-cycles OR cycles                               [Hardware event]
>   instructions                                       [Hardware event]
>   alignment-faults                                   [Software event]
>   bpf-output                                         [Software event]
>   cgroup-switches                                    [Software event]
>   context-switches OR cs                             [Software event]
>   cpu-clock                                          [Software event]
>   cpu-migrations OR migrations                       [Software event]
>   dummy                                              [Software event]
>   emulation-faults                                   [Software event]
>   major-faults                                       [Software event]
>   minor-faults                                       [Software event]
>   page-faults OR faults                              [Software event]
>   task-clock                                         [Software event]
>   duration_time                                      [Tool event]
>   user_time                                          [Tool event]
>   system_time                                        [Tool event]
>
> armv8_cortex_a53:
>   L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/
>   L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/
>   L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/
>   L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/
>   L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/
>   dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/
>   iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/
>   branch-loads OR armv8_cortex_a53/branch-loads/
>   branch-load-misses OR armv8_cortex_a53/branch-load-misses/
>   node-loads OR armv8_cortex_a53/node-loads/
>   node-stores OR armv8_cortex_a53/node-stores/
>   br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event]
>   br_mis_pred OR armv8_cortex_a53/br_mis_pred/       [Kernel PMU event]
>   br_pred OR armv8_cortex_a53/br_pred/               [Kernel PMU event]
>   bus_access OR armv8_cortex_a53/bus_access/         [Kernel PMU event]
>   bus_cycles OR armv8_cortex_a53/bus_cycles/         [Kernel PMU event]
>   cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event]
>   cpu_cycles OR armv8_cortex_a53/cpu_cycles/         [Kernel PMU event]
>   exc_return OR armv8_cortex_a53/exc_return/         [Kernel PMU event]
>
> [alarm@archl-librecm ~]$ perf stat -B -e
> cache-references,cache-misses,cycles,instructions,branches,faults,migrations
> sleep 5
>
>  Performance counter stats for 'sleep 5':
>
>              52794      cache-references:u
>               2311      cache-misses:u                   #    4.38% of
> all cache refs
>             480343      cycles:u
>             140018      instructions:u                   #    0.29
> insn per cycle
>              15012      branches:u
>                 46      faults:u
>                  0      migrations:u
>
>        5.008073381 seconds time elapsed
>
>        0.000000000 seconds user
>        0.006952000 seconds sys
>
I just wanted to revisit this patch series with some updates on
Arm Cortex A53 TRM, here are the L1 and L2 Cache size details.

[1] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en
[2] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[3] https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache

Thanks
-Anand

[PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC

[Anand Moon]

As per S905X3 datasheet add missing cache information to the Amlogic
SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.

- Each Cortex-A55 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L3 cache.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Datasheet
[0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf
[1] https://en.wikipedia.org/wiki/ARM_Cortex-A55
---
 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++----
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 643f94d9d08e..403443e782e4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -55,7 +55,13 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l3>;
 			#cooling-cells = <2>;
 		};
 
@@ -64,7 +70,13 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l3>;
 			#cooling-cells = <2>;
 		};
 
@@ -73,7 +85,13 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l3>;
 			#cooling-cells = <2>;
 		};
 
@@ -82,14 +100,23 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l3>;
 			#cooling-cells = <2>;
 		};
 
-		l2: l2-cache0 {
+		l3: l3-cache0 {
 			compatible = "cache";
-			cache-level = <2>;
+			cache-level = <3>;
 			cache-unified;
+			cache-size = <0x7d000>; /* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 
-- 
2.43.0


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Re: [PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC

[Neil Armstrong]

On 05/02/2024 18:19, Anand Moon wrote:
> As per S905X3 datasheet add missing cache information to the Amlogic
> SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
> 
> - Each Cortex-A55 core has 32KB of L1 instruction cache available and
> 	32KB of L1 data cache available.
> - Along with 512KB Unified L3 cache.

This 512K number is for the NPU, AFAIK the CPU L3 Cache size isn't specified in the datasheet

> 
> To improve system performance.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> Datasheet
> [0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf
> [1] https://en.wikipedia.org/wiki/ARM_Cortex-A55
> ---
>   arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++----
>   1 file changed, 33 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> index 643f94d9d08e..403443e782e4 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> @@ -55,7 +55,13 @@ cpu0: cpu@0 {
>   			compatible = "arm,cortex-a55";
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l3>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -64,7 +70,13 @@ cpu1: cpu@1 {
>   			compatible = "arm,cortex-a55";
>   			reg = <0x0 0x1>;
>   			enable-method = "psci";
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l3>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -73,7 +85,13 @@ cpu2: cpu@2 {
>   			compatible = "arm,cortex-a55";
>   			reg = <0x0 0x2>;
>   			enable-method = "psci";
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l3>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -82,14 +100,23 @@ cpu3: cpu@3 {
>   			compatible = "arm,cortex-a55";
>   			reg = <0x0 0x3>;
>   			enable-method = "psci";
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l3>;
>   			#cooling-cells = <2>;
>   		};
>   
> -		l2: l2-cache0 {
> +		l3: l3-cache0 {
>   			compatible = "cache";
> -			cache-level = <2>;
> +			cache-level = <3>;
>   			cache-unified;
> +			cache-size = <0x7d000>; /* L2. 512 KB */

Comment should be L3 here

> +			cache-line-size = <64>;
> +			cache-sets = <512>;
>   		};
>   	};
>   

Thanks,
Neil


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Re: [PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC

[Anand Moon]

Hi Neil,

On Tue, 6 Feb 2024 at 14:24, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 05/02/2024 18:19, Anand Moon wrote:
> > As per S905X3 datasheet add missing cache information to the Amlogic
> > SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
> >
> > - Each Cortex-A55 core has 32KB of L1 instruction cache available and
> >       32KB of L1 data cache available.
> > - Along with 512KB Unified L3 cache.
>
> This 512K number is for the NPU, AFAIK the CPU L3 Cache size isn't specified in the datasheet
>
OK,

As per Arm Cotex A55 TRM it supports cache.
[0] https://developer.arm.com/documentation/100442/0200/Functional-description/Introduction-to-the-Cortex-A55-core/Implementation-options

As per the datasheet
[1] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf

TheCortex™-A55M subsystem of the chipisa high-performance,
low-power,ARM macro cell with an L1 and L3
cache sub system that provide full virtual memory capabilities.

Best way to let the Amlogic SoC members comment on the CPU  L1/ //L2/
L3 cache size.
But with the lack of pref PMU events we cannot test this feature.

[root@odroid-c4 alarm]# perf list

List of pre-defined events (to be used in -e or -M):

  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  cgroup-switches                                    [Software event]
  context-switches OR cs                             [Software event]

List of pre-defined events (to be used in -e or -M):

  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  cgroup-switches                                    [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]
  rNNN                                               [Raw hardware event descri>
  cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descri>
       [(see 'man perf-list' on how to encode it)]
  mem:<addr>[/len][:access]                          [Hardware breakpoint]
  alarmtimer:alarmtimer_cancel                       [Tracepoint event]
  alarmtimer:alarmtimer_fired                        [Tracepoint event]
  alarmtimer:alarmtimer_start                        [Tracepoint event]
  alarmtimer:alarmtimer_suspend                      [Tracepoint event]
  asoc:snd_soc_bias_level_done                       [Tracepoint event]
  asoc:snd_soc_bias_level_start                      [Tracepoint event]
  asoc:snd_soc_dapm_connected                        [Tracepoint event]
  asoc:snd_soc_dapm_done                             [Tracepoint event]
  asoc:snd_soc_dapm_path                             [Tracepoint event]
  asoc:snd_soc_dapm_start                            [Tracepoint event]
  asoc:snd_soc_dapm_walk_done                        [Tracepoint event]
  asoc:snd_soc_dapm_widget_event_done                [Tracepoint event]
  asoc:snd_soc_dapm_widget_event_start               [Tracepoint event]
  asoc:snd_soc_dapm_widget_power                     [Tracepoint event]



Thanks



-Anand

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[PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

[Anand Moon]

As per the S905X2 datasheet add missing cache information to the Amlogic
G12A SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
nence used the same cache size as S905 and S905X.
---
 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 543e70669df5..6e1e3a3f5f18 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -17,6 +17,12 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			#cooling-cells = <2>;
 		};
@@ -26,6 +32,12 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			#cooling-cells = <2>;
 		};
@@ -35,6 +47,12 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			#cooling-cells = <2>;
 		};
@@ -44,6 +62,12 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
 			next-level-cache = <&l2>;
 			#cooling-cells = <2>;
 		};
@@ -52,6 +76,9 @@ l2: l2-cache0 {
 			compatible = "cache";
 			cache-level = <2>;
 			cache-unified;
+			cache-size = <0x7d000>; /* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 
-- 
2.43.0


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Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

[Viacheslav]

Hi!

You missed the AXG family with the Cortex-A53 CPU. The datasheet does 
not provide information on cache sizes. Given that the A113X/A113D are 
equipped with the Arm Cortex-A53 processor, it is assumed they use the 
same cache size as the S905/S905X/S905X2 models.

05/02/2024 20.19, Anand Moon wrote:
> As per the S905X2 datasheet add missing cache information to the Amlogic
> G12A SoC.
> 
> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
> 	32KB of L1 data cache available.
> - Along with 512KB Unified L2 cache.
> 
> To improve system performance.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
> nence used the same cache size as S905 and S905X.
> ---
>   arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
>   1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 543e70669df5..6e1e3a3f5f18 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -17,6 +17,12 @@ cpu0: cpu@0 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
>   			next-level-cache = <&l2>;
>   			#cooling-cells = <2>;
>   		};
> @@ -26,6 +32,12 @@ cpu1: cpu@1 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x1>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
>   			next-level-cache = <&l2>;
>   			#cooling-cells = <2>;
>   		};
> @@ -35,6 +47,12 @@ cpu2: cpu@2 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x2>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
>   			next-level-cache = <&l2>;
>   			#cooling-cells = <2>;
>   		};
> @@ -44,6 +62,12 @@ cpu3: cpu@3 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x3>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
>   			next-level-cache = <&l2>;
>   			#cooling-cells = <2>;
>   		};
> @@ -52,6 +76,9 @@ l2: l2-cache0 {
>   			compatible = "cache";
>   			cache-level = <2>;
>   			cache-unified;
> +			cache-size = <0x7d000>; /* L2. 512 KB */
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
>   		};
>   	};
>   


Best regards,
--
Viacheslav Bocharov <adeep@lexina.in>

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Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

[Christian Hewitt]

> On 6 Feb 2024, at 11:48 am, Viacheslav <adeep@lexina.in> wrote:
> 
> You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.

GXM is also missing, and also using A53 cores.

Christian

> 05/02/2024 20.19, Anand Moon wrote:
>> As per the S905X2 datasheet add missing cache information to the Amlogic
>> G12A SoC.
>> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
>> 32KB of L1 data cache available.
>> - Along with 512KB Unified L2 cache.
>> To improve system performance.
>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> ---
>> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
>> nence used the same cache size as S905 and S905X.
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
>>  1 file changed, 27 insertions(+)
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 543e70669df5..6e1e3a3f5f18 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -17,6 +17,12 @@ cpu0: cpu@0 {
>>   compatible = "arm,cortex-a53";
>>   reg = <0x0 0x0>;
>>   enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>>   next-level-cache = <&l2>;
>>   #cooling-cells = <2>;
>>   };
>> @@ -26,6 +32,12 @@ cpu1: cpu@1 {
>>   compatible = "arm,cortex-a53";
>>   reg = <0x0 0x1>;
>>   enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>>   next-level-cache = <&l2>;
>>   #cooling-cells = <2>;
>>   };
>> @@ -35,6 +47,12 @@ cpu2: cpu@2 {
>>   compatible = "arm,cortex-a53";
>>   reg = <0x0 0x2>;
>>   enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>>   next-level-cache = <&l2>;
>>   #cooling-cells = <2>;
>>   };
>> @@ -44,6 +62,12 @@ cpu3: cpu@3 {
>>   compatible = "arm,cortex-a53";
>>   reg = <0x0 0x3>;
>>   enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>>   next-level-cache = <&l2>;
>>   #cooling-cells = <2>;
>>   };
>> @@ -52,6 +76,9 @@ l2: l2-cache0 {
>>   compatible = "cache";
>>   cache-level = <2>;
>>   cache-unified;
>> + cache-size = <0x7d000>; /* L2. 512 KB */
>> + cache-line-size = <64>;
>> + cache-sets = <512>;
>>   };
>>   };
>>  
> 
> 
> Best regards,
> --
> Viacheslav Bocharov <adeep@lexina.in>
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic



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Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

[Anand Moon]

Hi Christian / Viacheslav,

On Tue, 6 Feb 2024 at 13:23, Christian Hewitt
<christianshewitt@gmail.com> wrote:
>
> > On 6 Feb 2024, at 11:48 am, Viacheslav <adeep@lexina.in> wrote:
> >
> > You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.
>
> GXM is also missing, and also using A53 cores.
>
> Christian
>

This patch is valid if the hardware supports perf PMU events, see below
I dont have the hardware.

Best way to let the Amlogic SoC members comment on the CPU  L1/ /L2 cache size.
But with the lack of pref PMU events we cannot test this feature.

alarm@archl-librecm ~]$ sudo perf list

List of pre-defined events (to be used in -e or -M):

  branch-instructions OR branches                    [Hardware event]
  branch-misses                                      [Hardware event]
  bus-cycles                                         [Hardware event]
  cache-misses                                       [Hardware event]
  cache-references                                   [Hardware event]
  cpu-cycles OR cycles                               [Hardware event]
  instructions                                       [Hardware event]
  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  cgroup-switches                                    [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]

armv8_cortex_a53:
  L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/
  L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/
  L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/
  L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/
  L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/
  dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/
  iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/
  branch-loads OR armv8_cortex_a53/branch-loads/
  branch-load-misses OR armv8_cortex_a53/branch-load-misses/
  node-loads OR armv8_cortex_a53/node-loads/
  node-stores OR armv8_cortex_a53/node-stores/
  br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event]
  br_mis_pred OR armv8_cortex_a53/br_mis_pred/       [Kernel PMU event]
  br_pred OR armv8_cortex_a53/br_pred/               [Kernel PMU event]
  bus_access OR armv8_cortex_a53/bus_access/         [Kernel PMU event]
  bus_cycles OR armv8_cortex_a53/bus_cycles/         [Kernel PMU event]
  cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event]
  cpu_cycles OR armv8_cortex_a53/cpu_cycles/         [Kernel PMU event]
  exc_return OR armv8_cortex_a53/exc_return/         [Kernel PMU event]




> >
> > Best regards,
> > --
> > Viacheslav Bocharov <adeep@lexina.in>
> >
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
>

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[PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[Anand Moon]

As per S922X datasheet add missing cache information to the Amlogic
S922X SoC.

- Each Cortex-A53 core has 32 KB of instruction cache and
	32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
	64 KB of L1 data cache available.
- The little (A53) cluster has 512 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
[0] https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
[1] https://en.wikipedia.org/wiki/ARM_Cortex-A73
[2] https://en.wikipedia.org/wiki/ARM_Cortex-A53
---
 arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index 86e6ceb31d5e..624c6fd763ac 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -49,7 +49,13 @@ cpu0: cpu@0 {
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <592>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 			#cooling-cells = <2>;
 		};
 
@@ -59,7 +65,13 @@ cpu1: cpu@1 {
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <592>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 			#cooling-cells = <2>;
 		};
 
@@ -69,7 +81,13 @@ cpu100: cpu@100 {
 			reg = <0x0 0x100>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 
@@ -79,7 +97,13 @@ cpu101: cpu@101 {
 			reg = <0x0 0x101>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 
@@ -89,7 +113,13 @@ cpu102: cpu@102 {
 			reg = <0x0 0x102>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 
@@ -99,14 +129,32 @@ cpu103: cpu@103 {
 			reg = <0x0 0x103>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
-			next-level-cache = <&l2>;
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 
-		l2: l2-cache0 {
+		l2_cache_l: l2-cache-cluster0 {
 			compatible = "cache";
 			cache-level = <2>;
 			cache-unified;
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
+
+		l2_cache_b: l2-cache-cluster1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 };
-- 
2.43.0


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Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[Neil Armstrong]

On 05/02/2024 18:19, Anand Moon wrote:
> As per S922X datasheet add missing cache information to the Amlogic
> S922X SoC.
> 
> - Each Cortex-A53 core has 32 KB of instruction cache and
> 	32 KB of L1 data cache available.
> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> 	64 KB of L1 data cache available.
> - The little (A53) cluster has 512 KB of unified L2 cache available.
> - The big (A73) cluster has 1 MB of unified L2 cache available.

Datasheet says:
The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53

And there's no indication of the L1 or L2 cache sizes.

Neil

> 
> To improve system performance.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> [0] https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
> [1] https://en.wikipedia.org/wiki/ARM_Cortex-A73
> [2] https://en.wikipedia.org/wiki/ARM_Cortex-A53
> ---
>   arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++---
>   1 file changed, 55 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> index 86e6ceb31d5e..624c6fd763ac 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> @@ -49,7 +49,13 @@ cpu0: cpu@0 {
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <592>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -59,7 +65,13 @@ cpu1: cpu@1 {
>   			reg = <0x0 0x1>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <592>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -69,7 +81,13 @@ cpu100: cpu@100 {
>   			reg = <0x0 0x100>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <1024>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -79,7 +97,13 @@ cpu101: cpu@101 {
>   			reg = <0x0 0x101>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <1024>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -89,7 +113,13 @@ cpu102: cpu@102 {
>   			reg = <0x0 0x102>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <1024>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -99,14 +129,32 @@ cpu103: cpu@103 {
>   			reg = <0x0 0x103>;
>   			enable-method = "psci";
>   			capacity-dmips-mhz = <1024>;
> -			next-level-cache = <&l2>;
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> -		l2: l2-cache0 {
> +		l2_cache_l: l2-cache-cluster0 {
>   			compatible = "cache";
>   			cache-level = <2>;
>   			cache-unified;
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
> +
> +		l2_cache_b: l2-cache-cluster1 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
>   		};
>   	};
>   };


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Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[Anand Moon]

Hi Neil,

On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 05/02/2024 18:19, Anand Moon wrote:
> > As per S922X datasheet add missing cache information to the Amlogic
> > S922X SoC.
> >
> > - Each Cortex-A53 core has 32 KB of instruction cache and
> >       32 KB of L1 data cache available.
> > - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> >       64 KB of L1 data cache available.
> > - The little (A53) cluster has 512 KB of unified L2 cache available.
> > - The big (A73) cluster has 1 MB of unified L2 cache available.
>
> Datasheet says:
> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
>
Ok,

Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
the architecture with some improvements in cache features
hence I update the changes accordingly.
Also, I checked this in the ARM documentation earlier on this.

> And there's no indication of the L1 or L2 cache sizes.

What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
L1 and L2 cache size since it is part of the core features.
but I opted for these size values from a Wikipedia article.

On my Odroid N2+, I observe the following.

I have also done some testing on the stress-ng to verify this.

alarm@archl-on2:~$ lscpu
Architecture:           aarch64
  CPU op-mode(s):       32-bit, 64-bit
  Byte Order:           Little Endian
CPU(s):                 6
  On-line CPU(s) list:  0-5
Vendor ID:              ARM
  Model name:           Cortex-A53
    Model:              4
    Thread(s) per core: 1
    Core(s) per socket: 2
    Socket(s):          1
    Stepping:           r0p4
    CPU(s) scaling MHz: 100%
    CPU max MHz:        1800.0000
    CPU min MHz:        1000.0000
    BogoMIPS:           48.00
    Flags:              fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
  Model name:           Cortex-A73
    Model:              2
    Thread(s) per core: 1
    Core(s) per socket: 4
    Socket(s):          1
    Stepping:           r0p2
    CPU(s) scaling MHz: 63%
    CPU max MHz:        2208.0000
    CPU min MHz:        1000.0000
    BogoMIPS:           48.00
    Flags:              fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
Caches (sum of all):
  L1d:                  320 KiB (6 instances)
  L1i:                  320 KiB (6 instances)
  L2:                   1.5 MiB (2 instances)
NUMA:
  NUMA node(s):         1
  NUMA node0 CPU(s):    0-5
Vulnerabilities:
  Gather data sampling: Not affected
  Itlb multihit:        Not affected
  L1tf:                 Not affected
  Mds:                  Not affected
  Meltdown:             Not affected
  Mmio stale data:      Not affected
  Retbleed:             Not affected
  Spec rstack overflow: Not affected
  Spec store bypass:    Vulnerable
  Spectre v1:           Mitigation; __user pointer sanitization
  Spectre v2:           Vulnerable
  Srbds:                Not affected
  Tsx async abort:      Not affected
alarm@archl-on2:~$

alarm@archl-on2:~$ lstopo-no-graphics
Machine (3659MB total)
  Package L#0
    NUMANode L#0 (P#0 3659MB)
    L2 L#0 (512KB)
      L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
    L2 L#1 (1024KB)
      L1d L#2 (64KB) + L1i L#2 (64KB) + Core L#2 + PU L#2 (P#2)
      L1d L#3 (64KB) + L1i L#3 (64KB) + Core L#3 + PU L#3 (P#3)
      L1d L#4 (64KB) + L1i L#4 (64KB) + Core L#4 + PU L#4 (P#4)
      L1d L#5 (64KB) + L1i L#5 (64KB) + Core L#5 + PU L#5 (P#5)
  Block "mmcblk1boot0"
  Block "mmcblk1boot1"
  Block "mmcblk1"
  Net "eth0"

 >
> Neil
>

Thanks
-Anand

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Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[neil.armstrong]

On 06/02/2024 11:15, Anand Moon wrote:
> Hi Neil,
> 
> On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> On 05/02/2024 18:19, Anand Moon wrote:
>>> As per S922X datasheet add missing cache information to the Amlogic
>>> S922X SoC.
>>>
>>> - Each Cortex-A53 core has 32 KB of instruction cache and
>>>        32 KB of L1 data cache available.
>>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
>>>        64 KB of L1 data cache available.
>>> - The little (A53) cluster has 512 KB of unified L2 cache available.
>>> - The big (A73) cluster has 1 MB of unified L2 cache available.
>>
>> Datasheet says:
>> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
>> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
>>
> Ok,
> 
> Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
> the architecture with some improvements in cache features
> hence I update the changes accordingly.
> Also, I checked this in the ARM documentation earlier on this.

I don't understand, Amlogic states it's a shared L2 cache, but you trust
the ARM documentation instead ???

> 
>> And there's no indication of the L1 or L2 cache sizes.
> 
> What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
> L1 and L2 cache size since it is part of the core features.
> but I opted for these size values from a Wikipedia article.
> 
> On my Odroid N2+, I observe the following.
> 
> I have also done some testing on the stress-ng to verify this.


Ok I don't feel confident adding numbers that comes out of thin air,
and even more since they are only shared to userspace.

I think we should only add the numbers which are 100% sure

> 
> alarm@archl-on2:~$ lscpu
> Architecture:           aarch64
>    CPU op-mode(s):       32-bit, 64-bit
>    Byte Order:           Little Endian
> CPU(s):                 6
>    On-line CPU(s) list:  0-5
> Vendor ID:              ARM
>    Model name:           Cortex-A53
>      Model:              4
>      Thread(s) per core: 1
>      Core(s) per socket: 2
>      Socket(s):          1
>      Stepping:           r0p4
>      CPU(s) scaling MHz: 100%
>      CPU max MHz:        1800.0000
>      CPU min MHz:        1000.0000
>      BogoMIPS:           48.00
>      Flags:              fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
>    Model name:           Cortex-A73
>      Model:              2
>      Thread(s) per core: 1
>      Core(s) per socket: 4
>      Socket(s):          1
>      Stepping:           r0p2
>      CPU(s) scaling MHz: 63%
>      CPU max MHz:        2208.0000
>      CPU min MHz:        1000.0000
>      BogoMIPS:           48.00
>      Flags:              fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
> Caches (sum of all):
>    L1d:                  320 KiB (6 instances)
>    L1i:                  320 KiB (6 instances)
>    L2:                   1.5 MiB (2 instances)
> NUMA:
>    NUMA node(s):         1
>    NUMA node0 CPU(s):    0-5
> Vulnerabilities:
>    Gather data sampling: Not affected
>    Itlb multihit:        Not affected
>    L1tf:                 Not affected
>    Mds:                  Not affected
>    Meltdown:             Not affected
>    Mmio stale data:      Not affected
>    Retbleed:             Not affected
>    Spec rstack overflow: Not affected
>    Spec store bypass:    Vulnerable
>    Spectre v1:           Mitigation; __user pointer sanitization
>    Spectre v2:           Vulnerable
>    Srbds:                Not affected
>    Tsx async abort:      Not affected
> alarm@archl-on2:~$
> 
> alarm@archl-on2:~$ lstopo-no-graphics
> Machine (3659MB total)
>    Package L#0
>      NUMANode L#0 (P#0 3659MB)
>      L2 L#0 (512KB)
>        L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
>        L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
>      L2 L#1 (1024KB)
>        L1d L#2 (64KB) + L1i L#2 (64KB) + Core L#2 + PU L#2 (P#2)
>        L1d L#3 (64KB) + L1i L#3 (64KB) + Core L#3 + PU L#3 (P#3)
>        L1d L#4 (64KB) + L1i L#4 (64KB) + Core L#4 + PU L#4 (P#4)
>        L1d L#5 (64KB) + L1i L#5 (64KB) + Core L#5 + PU L#5 (P#5)
>    Block "mmcblk1boot0"
>    Block "mmcblk1boot1"
>    Block "mmcblk1"
>    Net "eth0"

This looks pretty, but let's keep exporting verified data.

> 
>   >
>> Neil
>>
> 
> Thanks
> -Anand


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Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[Anand Moon]

Hi Niel,

On Tue, 6 Feb 2024 at 20:31, <neil.armstrong@linaro.org> wrote:
>
> On 06/02/2024 11:15, Anand Moon wrote:
> > Hi Neil,
> >
> > On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote:
> >>
> >> On 05/02/2024 18:19, Anand Moon wrote:
> >>> As per S922X datasheet add missing cache information to the Amlogic
> >>> S922X SoC.
> >>>
> >>> - Each Cortex-A53 core has 32 KB of instruction cache and
> >>>        32 KB of L1 data cache available.
> >>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> >>>        64 KB of L1 data cache available.
> >>> - The little (A53) cluster has 512 KB of unified L2 cache available.
> >>> - The big (A73) cluster has 1 MB of unified L2 cache available.
> >>
> >> Datasheet says:
> >> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
> >> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
> >>
> > Ok,
> >
> > Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
> > the architecture with some improvements in cache features
> > hence I update the changes accordingly.
> > Also, I checked this in the ARM documentation earlier on this.
>
> I don't understand, Amlogic states it's a shared L2 cache, but you trust
> the ARM documentation instead ???

Yes please find the Cortex™-A73 TRM
L1 Cache
https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en
L2 Cache
https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en
>
> >
> >> And there's no indication of the L1 or L2 cache sizes.
> >
> > What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
> > L1 and L2 cache size since it is part of the core features.
> > but I opted for these size values from a Wikipedia article.
> >
> > On my Odroid N2+, I observe the following.
> >
> > I have also done some testing on the stress-ng to verify this.
>
>
> Ok I don't feel confident adding numbers that comes out of thin air,
> and even more since they are only shared to userspace.
>
> I think we should only add the numbers which are 100% sure

Best way to let the Amlogic SoC members comment on the CPU  L1/ / L2 cache size.
But with the lack of pref PMU events we cannot test this feature.

>
>
> This looks pretty, but let's keep exporting verified data.
>

This CPU hardware supports cache this feature, but with missing PMU for this cpu
so its not getting listed hardware events like cache-misses cache-references

alarm@archl-on2:~$ sudo perf list
[sudo] password for alarm:

List of pre-defined events (to be used in -e or -M):

  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  cgroup-switches                                    [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]
  duration_time                                      [Tool event]
  user_time                                          [Tool event]
  system_time                                        [Tool event]
  meson_ddr_bw/chan_1_rw_bytes/                      [Kernel PMU event]
  meson_ddr_bw/chan_2_rw_bytes/                      [Kernel PMU event]
  meson_ddr_bw/chan_3_rw_bytes/                      [Kernel PMU event]
  meson_ddr_bw/chan_4_rw_bytes/                      [Kernel PMU event]
  meson_ddr_bw/total_rw_bytes/                       [Kernel PMU event]
  rNNN                                               [Raw hardware
event descriptor]
  cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware
event descriptor]
       [(see 'man perf-list' on how to encode it)]
  mem:<addr>[/len][:access]                          [Hardware breakpoint]
  alarmtimer:alarmtimer_cancel                       [Tracepoint event]
  alarmtimer:alarmtimer_fired                        [Tracepoint event]
  alarmtimer:alarmtimer_start                        [Tracepoint event]
  alarmtimer:alarmtimer_suspend                      [Tracepoint event]
  asoc:snd_soc_bias_level_done                       [Tracepoint event]
  asoc:snd_soc_bias_level_start                      [Tracepoint event]
  asoc:snd_soc_dapm_connected                        [Tracepoint event]
  asoc:snd_soc_dapm_done                             [Tracepoint event]
  asoc:snd_soc_dapm_path                             [Tracepoint event]
  asoc:snd_soc_dapm_start                            [Tracepoint event]
  asoc:snd_soc_dapm_walk_done                        [Tracepoint event]
  asoc:snd_soc_dapm_widget_event_done                [Tracepoint event]
  asoc:snd_soc_dapm_widget_event_start               [Tracepoint event]
  asoc:snd_soc_dapm_widget_power                     [Tracepoint event]
  asoc:snd_soc_jack_irq                              [Tracepoint event]
  asoc:snd_soc_jack_notify                           [Tracepoint event]
  asoc:snd_soc_jack_report                           [Tracepoint event]
  binder:binder_alloc_lru_end                        [Tracepoint event]
  binder:binder_alloc_lru_start                      [Tracepoint event]
  binder:binder_alloc_page_end                       [Tracepoint event]
  binder:binder_alloc_page_start                     [Tracepoint event]
  binder:binder_command                              [Tracepoint event]
  binder:binder_free_lru_end                         [Tracepoint event]
  binder:binder_free_lru_start                       [Tracepoint event]
  binder:binder_ioctl                                [Tracepoint event]
  binder:binder_ioctl_done                           [Tracepoint event]
  binder:binder_lock                                 [Tracepoint event]
  binder:binder_locked                               [Tracepoint event]
  binder:binder_read_done                            [Tracepoint event]
  binder:binder_return                               [Tracepoint event]
  binder:binder_transaction                          [Tracepoint event]
  binder:binder_transaction_alloc_buf                [Tracepoint event]
  binder:binder_transaction_buffer_release           [Tracepoint event]
  binder:binder_transaction_failed_buffer_release    [Tracepoint event]
  binder:binder_transaction_fd_recv                  [Tracepoint event]


[root@archl-on2 alarm]# perf stat -B -e
cache-references,cache-misses,cycles,instructions,branches,faults,migrations
sleep 5

 Performance counter stats for 'sleep 5':

   <not supported>      cache-references
   <not supported>      cache-misses
   <not supported>      cycles
   <not supported>      instructions
   <not supported>      branches
                56      faults
                 0      migrations

       5.003404106 seconds time elapsed

       0.003396000 seconds user
       0.000000000 seconds sys

Thanks



-Anand

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Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[Anand Moon]

Hi Neil,

On Tue, 27 Feb 2024 at 18:34, Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Niel,
>
> On Tue, 6 Feb 2024 at 20:31, <neil.armstrong@linaro.org> wrote:
> >
> > On 06/02/2024 11:15, Anand Moon wrote:
> > > Hi Neil,
> > >
> > > On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote:
> > >>
> > >> On 05/02/2024 18:19, Anand Moon wrote:
> > >>> As per S922X datasheet add missing cache information to the Amlogic
> > >>> S922X SoC.
> > >>>
> > >>> - Each Cortex-A53 core has 32 KB of instruction cache and
> > >>>        32 KB of L1 data cache available.
> > >>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> > >>>        64 KB of L1 data cache available.
> > >>> - The little (A53) cluster has 512 KB of unified L2 cache available.
> > >>> - The big (A73) cluster has 1 MB of unified L2 cache available.
> > >>
> > >> Datasheet says:
> > >> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
> > >> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
> > >>
> > > Ok,
> > >
> > > Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
> > > the architecture with some improvements in cache features
> > > hence I update the changes accordingly.
> > > Also, I checked this in the ARM documentation earlier on this.
> >
> > I don't understand, Amlogic states it's a shared L2 cache, but you trust
> > the ARM documentation instead ???
>
> Yes please find the Cortex™-A73 TRM
> L1 Cache
> https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en
> L2 Cache
> https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en
> >
> > >
> > >> And there's no indication of the L1 or L2 cache sizes.
> > >
> > > What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
> > > L1 and L2 cache size since it is part of the core features.
> > > but I opted for these size values from a Wikipedia article.
> > >
> > > On my Odroid N2+, I observe the following.
> > >
> > > I have also done some testing on the stress-ng to verify this.
> >
> >
> > Ok I don't feel confident adding numbers that comes out of thin air,
> > and even more since they are only shared to userspace.
> >
> > I think we should only add the numbers which are 100% sure
>
> Best way to let the Amlogic SoC members comment on the CPU  L1/ / L2 cache size.
> But with the lack of pref PMU events we cannot test this feature.
>
> >
> >
> > This looks pretty, but let's keep exporting verified data.
> >
I just wanted to revisit this patch series with some updates on

Here is where the Android TV provides the cache details.
[1] https://androidpctv.com/comparative-amlogic-s922x/

Amlogic S922X Hexa Core SoC has four ARM Cortex-A73 cores capable of
reaching 1.8Ghz
with 1MB L2 cache + 2 Cortex-A53 RAM processors with 256k L2 cache,

https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache

Also  Amlogic A311D processor utilizes a "big.LITTLE" architecture, combining:

Quad-core ARM Cortex-A73:
Each Cortex-A73 core has:
     64 KB L1 instruction cache 64 KB L1 data cache
The Cortex-A73 cluster shares a 1 MB unified L2 cache.

Dual-core ARM Cortex-A53:
Each Cortex-A53 core has:
  32 KB L1 instruction cache, 32 KB L1 data cache

The Cortex-A53 cluster shares a 512 KB unified L2 cache.

From what I understand, CPU caches are a core feature of the CPU.
Do you think I should update these patches and resend ?

Thanks
-Anand

Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

[neil.armstrong]

On 20/08/2025 16:00, Anand Moon wrote:
> Hi Neil,
> 
> On Tue, 27 Feb 2024 at 18:34, Anand Moon <linux.amoon@gmail.com> wrote:
>>
>> Hi Niel,
>>
>> On Tue, 6 Feb 2024 at 20:31, <neil.armstrong@linaro.org> wrote:
>>>
>>> On 06/02/2024 11:15, Anand Moon wrote:
>>>> Hi Neil,
>>>>
>>>> On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>>>>
>>>>> On 05/02/2024 18:19, Anand Moon wrote:
>>>>>> As per S922X datasheet add missing cache information to the Amlogic
>>>>>> S922X SoC.
>>>>>>
>>>>>> - Each Cortex-A53 core has 32 KB of instruction cache and
>>>>>>         32 KB of L1 data cache available.
>>>>>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
>>>>>>         64 KB of L1 data cache available.
>>>>>> - The little (A53) cluster has 512 KB of unified L2 cache available.
>>>>>> - The big (A73) cluster has 1 MB of unified L2 cache available.
>>>>>
>>>>> Datasheet says:
>>>>> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
>>>>> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
>>>>>
>>>> Ok,
>>>>
>>>> Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
>>>> the architecture with some improvements in cache features
>>>> hence I update the changes accordingly.
>>>> Also, I checked this in the ARM documentation earlier on this.
>>>
>>> I don't understand, Amlogic states it's a shared L2 cache, but you trust
>>> the ARM documentation instead ???
>>
>> Yes please find the Cortex™-A73 TRM
>> L1 Cache
>> https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en
>> L2 Cache
>> https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en
>>>
>>>>
>>>>> And there's no indication of the L1 or L2 cache sizes.
>>>>
>>>> What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
>>>> L1 and L2 cache size since it is part of the core features.
>>>> but I opted for these size values from a Wikipedia article.
>>>>
>>>> On my Odroid N2+, I observe the following.
>>>>
>>>> I have also done some testing on the stress-ng to verify this.
>>>
>>>
>>> Ok I don't feel confident adding numbers that comes out of thin air,
>>> and even more since they are only shared to userspace.
>>>
>>> I think we should only add the numbers which are 100% sure
>>
>> Best way to let the Amlogic SoC members comment on the CPU  L1/ / L2 cache size.
>> But with the lack of pref PMU events we cannot test this feature.
>>
>>>
>>>
>>> This looks pretty, but let's keep exporting verified data.
>>>
> I just wanted to revisit this patch series with some updates on
> 
> Here is where the Android TV provides the cache details.
> [1] https://androidpctv.com/comparative-amlogic-s922x/
> 
> Amlogic S922X Hexa Core SoC has four ARM Cortex-A73 cores capable of
> reaching 1.8Ghz
> with 1MB L2 cache + 2 Cortex-A53 RAM processors with 256k L2 cache,
> 
> https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache
> 
> Also  Amlogic A311D processor utilizes a "big.LITTLE" architecture, combining:
> 
> Quad-core ARM Cortex-A73:
> Each Cortex-A73 core has:
>       64 KB L1 instruction cache 64 KB L1 data cache
> The Cortex-A73 cluster shares a 1 MB unified L2 cache.
> 
> Dual-core ARM Cortex-A53:
> Each Cortex-A53 core has:
>    32 KB L1 instruction cache, 32 KB L1 data cache
> 
> The Cortex-A53 cluster shares a 512 KB unified L2 cache.
> 
>  From what I understand, CPU caches are a core feature of the CPU.
> Do you think I should update these patches and resend ?

Yes sure,

Neil

> 
> Thanks
> -Anand

[PATCHv1 5/5] arm64: dts: amlogic: Add cache information to the Amlogic A7 SoC

[Anand Moon]

As per A311D datasheet add missing cache information to the Amlogic A7 SoC.

- Each Cortex-A53 core has 32 KB of instruction cache and
	32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
	64 KB of L1 data cache available.
- The little (A53) cluster has 512 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.

To improve system performance.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
[0] https://dl.khadas.com/products/vim4/datasheet/a311d2_quick_reference_manual_v0.6.pdf
[1] https://en.wikipedia.org/wiki/ARM_Cortex-A73
[2] https://en.wikipedia.org/wiki/ARM_Cortex-A53
---
 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index a03c7667d2b6..72dedc40f460 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -52,6 +52,13 @@ cpu100: cpu@100 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 		};
 
 		cpu101: cpu@101{
@@ -59,6 +66,13 @@ cpu101: cpu@101{
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x101>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 		};
 
 		cpu102: cpu@102 {
@@ -66,6 +80,13 @@ cpu102: cpu@102 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x102>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 		};
 
 		cpu103: cpu@103 {
@@ -73,6 +94,13 @@ cpu103: cpu@103 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x103>;
 			enable-method = "psci";
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&l2_cache_l>;
 		};
 
 		cpu0: cpu@0 {
@@ -80,6 +108,13 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 		};
 
 		cpu1: cpu@1 {
@@ -87,6 +122,13 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 		};
 
 		cpu2: cpu@2 {
@@ -94,6 +136,13 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
 		};
 
 		cpu3: cpu@3 {
@@ -101,6 +150,31 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			d-cache-line-size = <64>;
+			d-cache-size = <0x10000>;
+			d-cache-sets = <64>;
+			i-cache-line-size = <64>;
+			i-cache-size = <0x10000>;
+			i-cache-sets = <64>;
+			next-level-cache = <&l2_cache_b>;
+		};
+
+		l2_cache_l: l2-cache-cluster0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
+
+		l2_cache_b: l2-cache-cluster1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
 		};
 	};
 
-- 
2.43.0


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Re: [PATCHv1 5/5] arm64: dts: amlogic: Add cache information to the Amlogic A7 SoC

[Neil Armstrong]

On 05/02/2024 18:19, Anand Moon wrote:
> As per A311D datasheet add missing cache information to the Amlogic A7 SoC.
> 
> - Each Cortex-A53 core has 32 KB of instruction cache and
> 	32 KB of L1 data cache available.
> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> 	64 KB of L1 data cache available.
> - The little (A53) cluster has 512 KB of unified L2 cache available.
> - The big (A73) cluster has 1 MB of unified L2 cache available.

Where did you get those numbers ? I can't find them.

Neil

> 
> To improve system performance.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> [0] https://dl.khadas.com/products/vim4/datasheet/a311d2_quick_reference_manual_v0.6.pdf
> [1] https://en.wikipedia.org/wiki/ARM_Cortex-A73
> [2] https://en.wikipedia.org/wiki/ARM_Cortex-A53
> ---
>   arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++
>   1 file changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index a03c7667d2b6..72dedc40f460 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -52,6 +52,13 @@ cpu100: cpu@100 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x100>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   		};
>   
>   		cpu101: cpu@101{
> @@ -59,6 +66,13 @@ cpu101: cpu@101{
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x101>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   		};
>   
>   		cpu102: cpu@102 {
> @@ -66,6 +80,13 @@ cpu102: cpu@102 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x102>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   		};
>   
>   		cpu103: cpu@103 {
> @@ -73,6 +94,13 @@ cpu103: cpu@103 {
>   			compatible = "arm,cortex-a53";
>   			reg = <0x0 0x103>;
>   			enable-method = "psci";
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&l2_cache_l>;
>   		};
>   
>   		cpu0: cpu@0 {
> @@ -80,6 +108,13 @@ cpu0: cpu@0 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   		};
>   
>   		cpu1: cpu@1 {
> @@ -87,6 +122,13 @@ cpu1: cpu@1 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x0 0x1>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   		};
>   
>   		cpu2: cpu@2 {
> @@ -94,6 +136,13 @@ cpu2: cpu@2 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x0 0x2>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
>   		};
>   
>   		cpu3: cpu@3 {
> @@ -101,6 +150,31 @@ cpu3: cpu@3 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x0 0x3>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x10000>;
> +			d-cache-sets = <64>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x10000>;
> +			i-cache-sets = <64>;
> +			next-level-cache = <&l2_cache_b>;
> +		};
> +
> +		l2_cache_l: l2-cache-cluster0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
> +
> +		l2_cache_b: l2-cache-cluster1 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
>   		};
>   	};
>   


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