From: Markus Schneider-Pargmann <msp@baylibre.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Santosh Shilimkar <ssantosh@kernel.org>
Cc: Andrew Davis <afd@ti.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Markus Schneider-Pargmann <msp@baylibre.com>
Subject: [PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes
Date: Tue, 6 Feb 2024 15:37:11 +0100 [thread overview]
Message-ID: <20240206143711.2410135-5-msp@baylibre.com> (raw)
In-Reply-To: <20240206143711.2410135-1-msp@baylibre.com>
Add efuse nodes describing chip variant and speed grade.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index fef76f52a52e..14419df43624 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -14,10 +14,44 @@ wkup_conf: syscon@43000000 {
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
+ wkup_efuse: efuse@0 {
+ compatible = "socionext,uniphier-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x200>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chip_manufacturer: jtagidmfg@14 {
+ reg = <0x14 0x2>;
+ bits = <1 11>;
+ };
+
+ chip_partno: jtagidpartno@15 {
+ reg = <0x15 0x3>;
+ bits = <4 16>;
+ };
+
+ chip_variant: jtagidvariant@17 {
+ reg = <0x17 0x1>;
+ bits = <4 4>;
+ };
+
+ chip_speed: jtaguseridspeed@18 {
+ reg = <0x18 0x4>;
+ bits = <6 5>;
+ };
+ };
+ };
+
chipid: chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
+ nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
+ nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
};
};
--
2.43.0
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next prev parent reply other threads:[~2024-02-06 14:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-06 14:37 [PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells Markus Schneider-Pargmann
2024-02-06 14:37 ` [PATCH 1/4] nvmem: core: Read into buffers larger than data Markus Schneider-Pargmann
2024-02-06 22:07 ` Srinivas Kandagatla
2024-02-06 14:37 ` [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells Markus Schneider-Pargmann
2024-02-06 18:23 ` Rob Herring
2024-02-06 18:43 ` Rob Herring
2024-02-14 9:31 ` Markus Schneider-Pargmann
2024-02-17 14:25 ` Krzysztof Kozlowski
2024-03-04 10:36 ` Markus Schneider-Pargmann
2024-03-05 7:43 ` Krzysztof Kozlowski
2024-03-05 11:17 ` Markus Schneider-Pargmann
2024-03-05 14:11 ` Krzysztof Kozlowski
2024-03-05 14:42 ` Andrew Davis
2024-03-05 17:01 ` Krzysztof Kozlowski
2024-03-05 17:41 ` Andrew Davis
2024-03-18 16:10 ` Markus Schneider-Pargmann
2024-02-07 7:58 ` Krzysztof Kozlowski
2024-02-06 14:37 ` [PATCH 3/4] soc: ti: k3-socinfo: Add support for nvmem cells Markus Schneider-Pargmann
2024-02-06 14:37 ` Markus Schneider-Pargmann [this message]
2024-02-06 17:48 ` [PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes Andrew Davis
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