[PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells

[PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells

[Markus Schneider-Pargmann]

Hi,

am62 has a number of efuse fields that are situated in the device range
of the current chipid device node. As other devices require these
information as well, I am trying to establish a new nvmem layout for the
information available in this register range.

In this series the conflicting chipid driver is updated to support
nvmem-cells and the chipid node gets the register range removed and
replaced with nvmem cells on am62.

In a follow-up series the opp table will be updated.

Best,
Markus

Markus Schneider-Pargmann (4):
  nvmem: core: Read into buffers larger than data
  dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells
  soc: ti: k3-socinfo: Add support for nvmem cells
  arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes

 .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++-
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi    | 36 +++++++++-
 drivers/nvmem/core.c                          |  6 +-
 drivers/soc/ti/k3-socinfo.c                   | 67 +++++++++++++------
 4 files changed, 107 insertions(+), 25 deletions(-)

-- 
2.43.0


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[PATCH 1/4] nvmem: core: Read into buffers larger than data

[Markus Schneider-Pargmann]

The actual size that nvmem is using internally on a specific platform
with a specific devicetree may not be known in the consumer code. The
maximum size may be available at the same time.

Allow the use of larger buffers in nvmem_cell_read_common() by setting
buffers that are too large to zero before copying into them.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
 drivers/nvmem/core.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index 980123fb4dde..6fa061ede605 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -1806,12 +1806,14 @@ static int nvmem_cell_read_common(struct device *dev, const char *cell_id,
 		nvmem_cell_put(cell);
 		return PTR_ERR(buf);
 	}
-	if (len != count) {
+	if (len > count) {
 		kfree(buf);
 		nvmem_cell_put(cell);
 		return -EINVAL;
+	} else if (len < count) {
+		memset(val + len, 0, count - len);
 	}
-	memcpy(val, buf, count);
+	memcpy(val, buf, len);
 	kfree(buf);
 	nvmem_cell_put(cell);
 
-- 
2.43.0


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Re: [PATCH 1/4] nvmem: core: Read into buffers larger than data

[Srinivas Kandagatla]

On 06/02/2024 14:37, Markus Schneider-Pargmann wrote:
> The actual size that nvmem is using internally on a specific platform
> with a specific devicetree may not be known in the consumer code. The
> maximum size may be available at the same time.
> 
> Allow the use of larger buffers in nvmem_cell_read_common() by setting
> buffers that are too large to zero before copying into them.
> 
Can you explain why can we not use nvmem_cell_read() ?



there is an other thread to add get_size
https://www.spinics.net/lists/kernel/msg5075254.html

> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
>   drivers/nvmem/core.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
> index 980123fb4dde..6fa061ede605 100644
> --- a/drivers/nvmem/core.c
> +++ b/drivers/nvmem/core.c
> @@ -1806,12 +1806,14 @@ static int nvmem_cell_read_common(struct device *dev, const char *cell_id,
>   		nvmem_cell_put(cell);
>   		return PTR_ERR(buf);
>   	}
> -	if (len != count) {
> +	if (len > count) {
>   		kfree(buf);
>   		nvmem_cell_put(cell);
>   		return -EINVAL;
> +	} else if (len < count) {
> +		memset(val + len, 0, count - len);
no please.. this really does not belong here.

--srini
>   	}
> -	memcpy(val, buf, count);
> +	memcpy(val, buf, len);
>   	kfree(buf);
>   	nvmem_cell_put(cell);
>   

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[PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Markus Schneider-Pargmann]

The information k3-socinfo requires is stored in an efuse area. This
area is required by other devices/drivers as well, so using nvmem-cells
can be a cleaner way to describe which information are used.

If nvmem-cells are supplied, the address range is not required.
Cells chipvariant, chippartno and chipmanufacturer are introduced to
cover all required information.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: Andrew Davis <afd@ti.com>
---
 .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
index dada28b47ea0..f085b7275b7d 100644
--- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
+++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
@@ -26,9 +26,24 @@ properties:
   reg:
     maxItems: 1
 
+  nvmem-cells:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  nvmem-cell-names:
+    items:
+      - const: chipvariant
+      - const: chippartno
+      - const: chipmanufacturer
+
 required:
   - compatible
-  - reg
+
+oneOf:
+  - required:
+      - reg
+  - required:
+      - nvmem-cells
+      - nvmem-cell-names
 
 additionalProperties: false
 
@@ -38,3 +53,9 @@ examples:
         compatible = "ti,am654-chipid";
         reg = <0x43000014 0x4>;
     };
+  - |
+    chipid: chipid@14 {
+        compatible = "ti,am654-chipid";
+        nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
+        nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
+    };
-- 
2.43.0


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Rob Herring]

On Tue, 06 Feb 2024 15:37:09 +0100, Markus Schneider-Pargmann wrote:
> The information k3-socinfo requires is stored in an efuse area. This
> area is required by other devices/drivers as well, so using nvmem-cells
> can be a cleaner way to describe which information are used.
> 
> If nvmem-cells are supplied, the address range is not required.
> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> cover all required information.
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Reviewed-by: Andrew Davis <afd@ti.com>
> ---
>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.example.dts:39.27-43.11: Warning (unit_address_vs_reg): /example-1/chipid@14: node has a unit name, but no reg or ranges property

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240206143711.2410135-3-msp@baylibre.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Rob Herring]

On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> The information k3-socinfo requires is stored in an efuse area. This
> area is required by other devices/drivers as well, so using nvmem-cells
> can be a cleaner way to describe which information are used.
> 
> If nvmem-cells are supplied, the address range is not required.
> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> cover all required information.
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Reviewed-by: Andrew Davis <afd@ti.com>
> ---
>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> index dada28b47ea0..f085b7275b7d 100644
> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> @@ -26,9 +26,24 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  nvmem-cells:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +  nvmem-cell-names:
> +    items:
> +      - const: chipvariant
> +      - const: chippartno
> +      - const: chipmanufacturer
> +
>  required:
>    - compatible
> -  - reg
> +
> +oneOf:
> +  - required:
> +      - reg
> +  - required:
> +      - nvmem-cells
> +      - nvmem-cell-names
>  
>  additionalProperties: false
>  
> @@ -38,3 +53,9 @@ examples:
>          compatible = "ti,am654-chipid";
>          reg = <0x43000014 0x4>;
>      };
> +  - |
> +    chipid: chipid@14 {
> +        compatible = "ti,am654-chipid";

This isn't compatible if you have a completely different way to access 
it. 


> +        nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
> +        nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
> +    };
> -- 
> 2.43.0
> 

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Markus Schneider-Pargmann]

Hi Rob,

On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> > The information k3-socinfo requires is stored in an efuse area. This
> > area is required by other devices/drivers as well, so using nvmem-cells
> > can be a cleaner way to describe which information are used.
> > 
> > If nvmem-cells are supplied, the address range is not required.
> > Cells chipvariant, chippartno and chipmanufacturer are introduced to
> > cover all required information.
> > 
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > Reviewed-by: Andrew Davis <afd@ti.com>
> > ---
> >  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
> >  1 file changed, 22 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > index dada28b47ea0..f085b7275b7d 100644
> > --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > @@ -26,9 +26,24 @@ properties:
> >    reg:
> >      maxItems: 1
> >  
> > +  nvmem-cells:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +  nvmem-cell-names:
> > +    items:
> > +      - const: chipvariant
> > +      - const: chippartno
> > +      - const: chipmanufacturer
> > +
> >  required:
> >    - compatible
> > -  - reg
> > +
> > +oneOf:
> > +  - required:
> > +      - reg
> > +  - required:
> > +      - nvmem-cells
> > +      - nvmem-cell-names
> >  
> >  additionalProperties: false
> >  
> > @@ -38,3 +53,9 @@ examples:
> >          compatible = "ti,am654-chipid";
> >          reg = <0x43000014 0x4>;
> >      };
> > +  - |
> > +    chipid: chipid@14 {
> > +        compatible = "ti,am654-chipid";
> 
> This isn't compatible if you have a completely different way to access 
> it. 

Thanks, it is not entirely clear to me how I could go forward with this?
Are you suggesting to use a different compatible? Or is it something
else I could do to proceed with this conversion?

Thank you!

Best,
Markus

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
> Hi Rob,
> 
> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>> The information k3-socinfo requires is stored in an efuse area. This
>>> area is required by other devices/drivers as well, so using nvmem-cells
>>> can be a cleaner way to describe which information are used.
>>>
>>> If nvmem-cells are supplied, the address range is not required.
>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>> cover all required information.
>>>
>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>> ---
>>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>> index dada28b47ea0..f085b7275b7d 100644
>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>> @@ -26,9 +26,24 @@ properties:
>>>    reg:
>>>      maxItems: 1
>>>  
>>> +  nvmem-cells:
>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>> +
>>> +  nvmem-cell-names:
>>> +    items:
>>> +      - const: chipvariant
>>> +      - const: chippartno
>>> +      - const: chipmanufacturer
>>> +
>>>  required:
>>>    - compatible
>>> -  - reg
>>> +
>>> +oneOf:
>>> +  - required:
>>> +      - reg
>>> +  - required:
>>> +      - nvmem-cells
>>> +      - nvmem-cell-names
>>>  
>>>  additionalProperties: false
>>>  
>>> @@ -38,3 +53,9 @@ examples:
>>>          compatible = "ti,am654-chipid";
>>>          reg = <0x43000014 0x4>;
>>>      };
>>> +  - |
>>> +    chipid: chipid@14 {
>>> +        compatible = "ti,am654-chipid";
>>
>> This isn't compatible if you have a completely different way to access 
>> it. 
> 
> Thanks, it is not entirely clear to me how I could go forward with this?
> Are you suggesting to use a different compatible? Or is it something
> else I could do to proceed with this conversion?

What you claim now, is that you have one device with entirely different
interfaces and programming model. So either this is not the same device
or you just wrote bindings to whatever you have in driver.

Nothing in commit msg explains this.

What you should do? Depends. If you just write bindings for driver, then
stop. It's a NAK. Instead write bindings for hardware.

If the first choice, just the hardware is somehow like this, then
explain in commit msg and device description, how this device can be
connected over other bus, not MMIO. You can draw some schematics in
commit msg explaining architecture etc.

Best regards,
Krzysztof


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Markus Schneider-Pargmann]

Hi,

On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
> > Hi Rob,
> > 
> > On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
> >> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> >>> The information k3-socinfo requires is stored in an efuse area. This
> >>> area is required by other devices/drivers as well, so using nvmem-cells
> >>> can be a cleaner way to describe which information are used.
> >>>
> >>> If nvmem-cells are supplied, the address range is not required.
> >>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> >>> cover all required information.
> >>>
> >>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> >>> Reviewed-by: Andrew Davis <afd@ti.com>
> >>> ---
> >>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
> >>>  1 file changed, 22 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>> index dada28b47ea0..f085b7275b7d 100644
> >>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>> @@ -26,9 +26,24 @@ properties:
> >>>    reg:
> >>>      maxItems: 1
> >>>  
> >>> +  nvmem-cells:
> >>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> >>> +
> >>> +  nvmem-cell-names:
> >>> +    items:
> >>> +      - const: chipvariant
> >>> +      - const: chippartno
> >>> +      - const: chipmanufacturer
> >>> +
> >>>  required:
> >>>    - compatible
> >>> -  - reg
> >>> +
> >>> +oneOf:
> >>> +  - required:
> >>> +      - reg
> >>> +  - required:
> >>> +      - nvmem-cells
> >>> +      - nvmem-cell-names
> >>>  
> >>>  additionalProperties: false
> >>>  
> >>> @@ -38,3 +53,9 @@ examples:
> >>>          compatible = "ti,am654-chipid";
> >>>          reg = <0x43000014 0x4>;
> >>>      };
> >>> +  - |
> >>> +    chipid: chipid@14 {
> >>> +        compatible = "ti,am654-chipid";
> >>
> >> This isn't compatible if you have a completely different way to access 
> >> it. 
> > 
> > Thanks, it is not entirely clear to me how I could go forward with this?
> > Are you suggesting to use a different compatible? Or is it something
> > else I could do to proceed with this conversion?
> 
> What you claim now, is that you have one device with entirely different
> interfaces and programming model. So either this is not the same device
> or you just wrote bindings to whatever you have in driver.
> 
> Nothing in commit msg explains this.
> 
> What you should do? Depends. If you just write bindings for driver, then
> stop. It's a NAK. Instead write bindings for hardware.
> 
> If the first choice, just the hardware is somehow like this, then
> explain in commit msg and device description, how this device can be
> connected over other bus, not MMIO. You can draw some schematics in
> commit msg explaining architecture etc.

Sorry the information provided in the commit message is not very clear.

The basic access to the registes is still MMIO. nvmem is used to have a
better abstraction and cleaner description of the hardware.

Currently most of the data is exported using the parent syscon device.
The relevant data is read-only and contained in a single register with
offset 0x14:
  - Chip variant
  - Chip part number
  - Chip manufacturer

There are more read-only registers in this section of address space.
These are relevant to other components as they define the operating
points for example. For the OPP table relevant are chip variant and chip
speed (which is in a different register).

Instead of devices refering to this whole register range of 0x20000 in
size, I would like to introduce this nvmem abstraction in between that
describes the information and can directly be referenced by the devices
that depend on it. In this case the above mentioned register with offset
0x14 is instead described as nvmem-layout like this:

	nvmem-layout {
		compatible = "fixed-layout";
		#address-cells = <1>;
		#size-cells = <1>;

		chip_manufacturer: jtagidmfg@14 {
			reg = <0x14 0x2>;
			bits = <1 11>;
		};

		chip_partno: jtagidpartno@15 {
			reg = <0x15 0x3>;
			bits = <4 16>;
		};

		chip_variant: jtagidvariant@17 {
			reg = <0x17 0x1>;
			bits = <4 4>;
		};

		chip_speed: jtaguseridspeed@18 {
			reg = <0x18 0x4>;
			bits = <6 5>;
		};

The underlying registers are still the same but they are not hidden
by the syscon phandles anymore.

The device that consumes this data would now use

	nvmem-cells = <&chip_variant>, <&chip_speed>;
	nvmem-cell-names = "chipvariant", "chipspeed";

instead of

	syscon = <&wkup_conf>;

Best,
Markus

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
> Hi,
> 
> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>> Hi Rob,
>>>
>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>> can be a cleaner way to describe which information are used.
>>>>>
>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>> cover all required information.
>>>>>
>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>>>> ---
>>>>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>    reg:
>>>>>      maxItems: 1
>>>>>  
>>>>> +  nvmem-cells:
>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>> +
>>>>> +  nvmem-cell-names:
>>>>> +    items:
>>>>> +      - const: chipvariant
>>>>> +      - const: chippartno
>>>>> +      - const: chipmanufacturer
>>>>> +
>>>>>  required:
>>>>>    - compatible
>>>>> -  - reg
>>>>> +
>>>>> +oneOf:
>>>>> +  - required:
>>>>> +      - reg
>>>>> +  - required:
>>>>> +      - nvmem-cells
>>>>> +      - nvmem-cell-names
>>>>>  
>>>>>  additionalProperties: false
>>>>>  
>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>          compatible = "ti,am654-chipid";
>>>>>          reg = <0x43000014 0x4>;
>>>>>      };
>>>>> +  - |
>>>>> +    chipid: chipid@14 {
>>>>> +        compatible = "ti,am654-chipid";
>>>>
>>>> This isn't compatible if you have a completely different way to access 
>>>> it. 
>>>
>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>> Are you suggesting to use a different compatible? Or is it something
>>> else I could do to proceed with this conversion?
>>
>> What you claim now, is that you have one device with entirely different
>> interfaces and programming model. So either this is not the same device
>> or you just wrote bindings to whatever you have in driver.
>>
>> Nothing in commit msg explains this.
>>
>> What you should do? Depends. If you just write bindings for driver, then
>> stop. It's a NAK. Instead write bindings for hardware.
>>
>> If the first choice, just the hardware is somehow like this, then
>> explain in commit msg and device description, how this device can be
>> connected over other bus, not MMIO. You can draw some schematics in
>> commit msg explaining architecture etc.
> 
> Sorry the information provided in the commit message is not very clear.
> 
> The basic access to the registes is still MMIO. nvmem is used to have a
> better abstraction and cleaner description of the hardware.
> 
> Currently most of the data is exported using the parent syscon device.
> The relevant data is read-only and contained in a single register with
> offset 0x14:
>   - Chip variant
>   - Chip part number
>   - Chip manufacturer
> 
> There are more read-only registers in this section of address space.
> These are relevant to other components as they define the operating
> points for example. For the OPP table relevant are chip variant and chip
> speed (which is in a different register).
> 
> Instead of devices refering to this whole register range of 0x20000 in

Whaaaaat?

> size, I would like to introduce this nvmem abstraction in between that
> describes the information and can directly be referenced by the devices
> that depend on it. In this case the above mentioned register with offset
> 0x14 is instead described as nvmem-layout like this:
> 
> 	nvmem-layout {
> 		compatible = "fixed-layout";
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 
> 		chip_manufacturer: jtagidmfg@14 {
> 			reg = <0x14 0x2>;
> 			bits = <1 11>;
> 		};
> 
> 		chip_partno: jtagidpartno@15 {
> 			reg = <0x15 0x3>;
> 			bits = <4 16>;
> 		};
> 
> 		chip_variant: jtagidvariant@17 {
> 			reg = <0x17 0x1>;
> 			bits = <4 4>;
> 		};
> 
> 		chip_speed: jtaguseridspeed@18 {
> 			reg = <0x18 0x4>;
> 			bits = <6 5>;
> 		};
> 
> The underlying registers are still the same but they are not hidden
> by the syscon phandles anymore.
> 
> The device that consumes this data would now use
> 
> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
> 	nvmem-cell-names = "chipvariant", "chipspeed";
> 
> instead of
> 
> 	syscon = <&wkup_conf>;

syscon allows you this as well - via phandle arguments.

nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
accessing regular MMIO registers of system-controller, regardless
whether they are read-only or not (regmap handles this nicely, BTW).
Although probably Apple efuses and few others can confuse here. It still
looks like you convert regular system-controller block into nvmem,
because you prefer that Linux driver abstraction...

Best regards,
Krzysztof


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Markus Schneider-Pargmann]

Hi Krzysztof,

On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
> > Hi,
> > 
> > On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
> >> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
> >>> Hi Rob,
> >>>
> >>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
> >>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> >>>>> The information k3-socinfo requires is stored in an efuse area. This
> >>>>> area is required by other devices/drivers as well, so using nvmem-cells
> >>>>> can be a cleaner way to describe which information are used.
> >>>>>
> >>>>> If nvmem-cells are supplied, the address range is not required.
> >>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> >>>>> cover all required information.
> >>>>>
> >>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> >>>>> Reviewed-by: Andrew Davis <afd@ti.com>
> >>>>> ---
> >>>>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
> >>>>>  1 file changed, 22 insertions(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>>>> index dada28b47ea0..f085b7275b7d 100644
> >>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> >>>>> @@ -26,9 +26,24 @@ properties:
> >>>>>    reg:
> >>>>>      maxItems: 1
> >>>>>  
> >>>>> +  nvmem-cells:
> >>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> >>>>> +
> >>>>> +  nvmem-cell-names:
> >>>>> +    items:
> >>>>> +      - const: chipvariant
> >>>>> +      - const: chippartno
> >>>>> +      - const: chipmanufacturer
> >>>>> +
> >>>>>  required:
> >>>>>    - compatible
> >>>>> -  - reg
> >>>>> +
> >>>>> +oneOf:
> >>>>> +  - required:
> >>>>> +      - reg
> >>>>> +  - required:
> >>>>> +      - nvmem-cells
> >>>>> +      - nvmem-cell-names
> >>>>>  
> >>>>>  additionalProperties: false
> >>>>>  
> >>>>> @@ -38,3 +53,9 @@ examples:
> >>>>>          compatible = "ti,am654-chipid";
> >>>>>          reg = <0x43000014 0x4>;
> >>>>>      };
> >>>>> +  - |
> >>>>> +    chipid: chipid@14 {
> >>>>> +        compatible = "ti,am654-chipid";
> >>>>
> >>>> This isn't compatible if you have a completely different way to access 
> >>>> it. 
> >>>
> >>> Thanks, it is not entirely clear to me how I could go forward with this?
> >>> Are you suggesting to use a different compatible? Or is it something
> >>> else I could do to proceed with this conversion?
> >>
> >> What you claim now, is that you have one device with entirely different
> >> interfaces and programming model. So either this is not the same device
> >> or you just wrote bindings to whatever you have in driver.
> >>
> >> Nothing in commit msg explains this.
> >>
> >> What you should do? Depends. If you just write bindings for driver, then
> >> stop. It's a NAK. Instead write bindings for hardware.
> >>
> >> If the first choice, just the hardware is somehow like this, then
> >> explain in commit msg and device description, how this device can be
> >> connected over other bus, not MMIO. You can draw some schematics in
> >> commit msg explaining architecture etc.
> > 
> > Sorry the information provided in the commit message is not very clear.
> > 
> > The basic access to the registes is still MMIO. nvmem is used to have a
> > better abstraction and cleaner description of the hardware.
> > 
> > Currently most of the data is exported using the parent syscon device.
> > The relevant data is read-only and contained in a single register with
> > offset 0x14:
> >   - Chip variant
> >   - Chip part number
> >   - Chip manufacturer
> > 
> > There are more read-only registers in this section of address space.
> > These are relevant to other components as they define the operating
> > points for example. For the OPP table relevant are chip variant and chip
> > speed (which is in a different register).
> > 
> > Instead of devices refering to this whole register range of 0x20000 in
> 
> Whaaaaat?
> 
> > size, I would like to introduce this nvmem abstraction in between that
> > describes the information and can directly be referenced by the devices
> > that depend on it. In this case the above mentioned register with offset
> > 0x14 is instead described as nvmem-layout like this:
> > 
> > 	nvmem-layout {
> > 		compatible = "fixed-layout";
> > 		#address-cells = <1>;
> > 		#size-cells = <1>;
> > 
> > 		chip_manufacturer: jtagidmfg@14 {
> > 			reg = <0x14 0x2>;
> > 			bits = <1 11>;
> > 		};
> > 
> > 		chip_partno: jtagidpartno@15 {
> > 			reg = <0x15 0x3>;
> > 			bits = <4 16>;
> > 		};
> > 
> > 		chip_variant: jtagidvariant@17 {
> > 			reg = <0x17 0x1>;
> > 			bits = <4 4>;
> > 		};
> > 
> > 		chip_speed: jtaguseridspeed@18 {
> > 			reg = <0x18 0x4>;
> > 			bits = <6 5>;
> > 		};
> > 
> > The underlying registers are still the same but they are not hidden
> > by the syscon phandles anymore.
> > 
> > The device that consumes this data would now use
> > 
> > 	nvmem-cells = <&chip_variant>, <&chip_speed>;
> > 	nvmem-cell-names = "chipvariant", "chipspeed";
> > 
> > instead of
> > 
> > 	syscon = <&wkup_conf>;
> 
> syscon allows you this as well - via phandle arguments.
> 
> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
> accessing regular MMIO registers of system-controller, regardless
> whether they are read-only or not (regmap handles this nicely, BTW).
> Although probably Apple efuses and few others can confuse here. It still
> looks like you convert regular system-controller block into nvmem,
> because you prefer that Linux driver abstraction...

The above mentioned data is set in the factory. There is other
non-volatile data, like device feature registers, in the same address
region, as well as OTP data like MAC and USB IDs. But it is not a pure
non-volatile memory region. The data is copied into these registers by
the ROM at boot.

Best,
Markus

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
> Hi Krzysztof,
> 
> On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
>> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
>>> Hi,
>>>
>>> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>>>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>>>> Hi Rob,
>>>>>
>>>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>>>> can be a cleaner way to describe which information are used.
>>>>>>>
>>>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>>>> cover all required information.
>>>>>>>
>>>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>>>>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>>>>>> ---
>>>>>>>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>>>    reg:
>>>>>>>      maxItems: 1
>>>>>>>  
>>>>>>> +  nvmem-cells:
>>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>>> +
>>>>>>> +  nvmem-cell-names:
>>>>>>> +    items:
>>>>>>> +      - const: chipvariant
>>>>>>> +      - const: chippartno
>>>>>>> +      - const: chipmanufacturer
>>>>>>> +
>>>>>>>  required:
>>>>>>>    - compatible
>>>>>>> -  - reg
>>>>>>> +
>>>>>>> +oneOf:
>>>>>>> +  - required:
>>>>>>> +      - reg
>>>>>>> +  - required:
>>>>>>> +      - nvmem-cells
>>>>>>> +      - nvmem-cell-names
>>>>>>>  
>>>>>>>  additionalProperties: false
>>>>>>>  
>>>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>>>          compatible = "ti,am654-chipid";
>>>>>>>          reg = <0x43000014 0x4>;
>>>>>>>      };
>>>>>>> +  - |
>>>>>>> +    chipid: chipid@14 {
>>>>>>> +        compatible = "ti,am654-chipid";
>>>>>>
>>>>>> This isn't compatible if you have a completely different way to access 
>>>>>> it. 
>>>>>
>>>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>>>> Are you suggesting to use a different compatible? Or is it something
>>>>> else I could do to proceed with this conversion?
>>>>
>>>> What you claim now, is that you have one device with entirely different
>>>> interfaces and programming model. So either this is not the same device
>>>> or you just wrote bindings to whatever you have in driver.
>>>>
>>>> Nothing in commit msg explains this.
>>>>
>>>> What you should do? Depends. If you just write bindings for driver, then
>>>> stop. It's a NAK. Instead write bindings for hardware.
>>>>
>>>> If the first choice, just the hardware is somehow like this, then
>>>> explain in commit msg and device description, how this device can be
>>>> connected over other bus, not MMIO. You can draw some schematics in
>>>> commit msg explaining architecture etc.
>>>
>>> Sorry the information provided in the commit message is not very clear.
>>>
>>> The basic access to the registes is still MMIO. nvmem is used to have a
>>> better abstraction and cleaner description of the hardware.
>>>
>>> Currently most of the data is exported using the parent syscon device.
>>> The relevant data is read-only and contained in a single register with
>>> offset 0x14:
>>>   - Chip variant
>>>   - Chip part number
>>>   - Chip manufacturer
>>>
>>> There are more read-only registers in this section of address space.
>>> These are relevant to other components as they define the operating
>>> points for example. For the OPP table relevant are chip variant and chip
>>> speed (which is in a different register).
>>>
>>> Instead of devices refering to this whole register range of 0x20000 in
>>
>> Whaaaaat?
>>
>>> size, I would like to introduce this nvmem abstraction in between that
>>> describes the information and can directly be referenced by the devices
>>> that depend on it. In this case the above mentioned register with offset
>>> 0x14 is instead described as nvmem-layout like this:
>>>
>>> 	nvmem-layout {
>>> 		compatible = "fixed-layout";
>>> 		#address-cells = <1>;
>>> 		#size-cells = <1>;
>>>
>>> 		chip_manufacturer: jtagidmfg@14 {
>>> 			reg = <0x14 0x2>;
>>> 			bits = <1 11>;
>>> 		};
>>>
>>> 		chip_partno: jtagidpartno@15 {
>>> 			reg = <0x15 0x3>;
>>> 			bits = <4 16>;
>>> 		};
>>>
>>> 		chip_variant: jtagidvariant@17 {
>>> 			reg = <0x17 0x1>;
>>> 			bits = <4 4>;
>>> 		};
>>>
>>> 		chip_speed: jtaguseridspeed@18 {
>>> 			reg = <0x18 0x4>;
>>> 			bits = <6 5>;
>>> 		};
>>>
>>> The underlying registers are still the same but they are not hidden
>>> by the syscon phandles anymore.
>>>
>>> The device that consumes this data would now use
>>>
>>> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
>>> 	nvmem-cell-names = "chipvariant", "chipspeed";
>>>
>>> instead of
>>>
>>> 	syscon = <&wkup_conf>;
>>
>> syscon allows you this as well - via phandle arguments.
>>
>> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
>> accessing regular MMIO registers of system-controller, regardless
>> whether they are read-only or not (regmap handles this nicely, BTW).
>> Although probably Apple efuses and few others can confuse here. It still
>> looks like you convert regular system-controller block into nvmem,
>> because you prefer that Linux driver abstraction...
> 
> The above mentioned data is set in the factory. There is other
> non-volatile data, like device feature registers, in the same address
> region, as well as OTP data like MAC and USB IDs. But it is not a pure
> non-volatile memory region. The data is copied into these registers by
> the ROM at boot.

Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.

Best regards,
Krzysztof


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Andrew Davis]

On 3/5/24 8:11 AM, Krzysztof Kozlowski wrote:
> On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
>> Hi Krzysztof,
>>
>> On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
>>> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
>>>> Hi,
>>>>
>>>> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>>>>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>>>>> Hi Rob,
>>>>>>
>>>>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>>>>> can be a cleaner way to describe which information are used.
>>>>>>>>
>>>>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>>>>> cover all required information.
>>>>>>>>
>>>>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>>>>>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>>>>>>> ---
>>>>>>>>   .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>>>>   1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>>>>     reg:
>>>>>>>>       maxItems: 1
>>>>>>>>   
>>>>>>>> +  nvmem-cells:
>>>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>>>> +
>>>>>>>> +  nvmem-cell-names:
>>>>>>>> +    items:
>>>>>>>> +      - const: chipvariant
>>>>>>>> +      - const: chippartno
>>>>>>>> +      - const: chipmanufacturer
>>>>>>>> +
>>>>>>>>   required:
>>>>>>>>     - compatible
>>>>>>>> -  - reg
>>>>>>>> +
>>>>>>>> +oneOf:
>>>>>>>> +  - required:
>>>>>>>> +      - reg
>>>>>>>> +  - required:
>>>>>>>> +      - nvmem-cells
>>>>>>>> +      - nvmem-cell-names
>>>>>>>>   
>>>>>>>>   additionalProperties: false
>>>>>>>>   
>>>>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>>>>           compatible = "ti,am654-chipid";
>>>>>>>>           reg = <0x43000014 0x4>;
>>>>>>>>       };
>>>>>>>> +  - |
>>>>>>>> +    chipid: chipid@14 {
>>>>>>>> +        compatible = "ti,am654-chipid";
>>>>>>>
>>>>>>> This isn't compatible if you have a completely different way to access
>>>>>>> it.
>>>>>>
>>>>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>>>>> Are you suggesting to use a different compatible? Or is it something
>>>>>> else I could do to proceed with this conversion?
>>>>>
>>>>> What you claim now, is that you have one device with entirely different
>>>>> interfaces and programming model. So either this is not the same device
>>>>> or you just wrote bindings to whatever you have in driver.
>>>>>
>>>>> Nothing in commit msg explains this.
>>>>>
>>>>> What you should do? Depends. If you just write bindings for driver, then
>>>>> stop. It's a NAK. Instead write bindings for hardware.
>>>>>
>>>>> If the first choice, just the hardware is somehow like this, then
>>>>> explain in commit msg and device description, how this device can be
>>>>> connected over other bus, not MMIO. You can draw some schematics in
>>>>> commit msg explaining architecture etc.
>>>>
>>>> Sorry the information provided in the commit message is not very clear.
>>>>
>>>> The basic access to the registes is still MMIO. nvmem is used to have a
>>>> better abstraction and cleaner description of the hardware.
>>>>
>>>> Currently most of the data is exported using the parent syscon device.
>>>> The relevant data is read-only and contained in a single register with
>>>> offset 0x14:
>>>>    - Chip variant
>>>>    - Chip part number
>>>>    - Chip manufacturer
>>>>
>>>> There are more read-only registers in this section of address space.
>>>> These are relevant to other components as they define the operating
>>>> points for example. For the OPP table relevant are chip variant and chip
>>>> speed (which is in a different register).
>>>>
>>>> Instead of devices refering to this whole register range of 0x20000 in
>>>
>>> Whaaaaat?
>>>
>>>> size, I would like to introduce this nvmem abstraction in between that
>>>> describes the information and can directly be referenced by the devices
>>>> that depend on it. In this case the above mentioned register with offset
>>>> 0x14 is instead described as nvmem-layout like this:
>>>>
>>>> 	nvmem-layout {
>>>> 		compatible = "fixed-layout";
>>>> 		#address-cells = <1>;
>>>> 		#size-cells = <1>;
>>>>
>>>> 		chip_manufacturer: jtagidmfg@14 {
>>>> 			reg = <0x14 0x2>;
>>>> 			bits = <1 11>;
>>>> 		};
>>>>
>>>> 		chip_partno: jtagidpartno@15 {
>>>> 			reg = <0x15 0x3>;
>>>> 			bits = <4 16>;
>>>> 		};
>>>>
>>>> 		chip_variant: jtagidvariant@17 {
>>>> 			reg = <0x17 0x1>;
>>>> 			bits = <4 4>;
>>>> 		};
>>>>
>>>> 		chip_speed: jtaguseridspeed@18 {
>>>> 			reg = <0x18 0x4>;
>>>> 			bits = <6 5>;
>>>> 		};
>>>>
>>>> The underlying registers are still the same but they are not hidden
>>>> by the syscon phandles anymore.
>>>>
>>>> The device that consumes this data would now use
>>>>
>>>> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
>>>> 	nvmem-cell-names = "chipvariant", "chipspeed";
>>>>
>>>> instead of
>>>>
>>>> 	syscon = <&wkup_conf>;
>>>
>>> syscon allows you this as well - via phandle arguments.
>>>
>>> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
>>> accessing regular MMIO registers of system-controller, regardless
>>> whether they are read-only or not (regmap handles this nicely, BTW).
>>> Although probably Apple efuses and few others can confuse here. It still
>>> looks like you convert regular system-controller block into nvmem,
>>> because you prefer that Linux driver abstraction...
>>
>> The above mentioned data is set in the factory. There is other
>> non-volatile data, like device feature registers, in the same address
>> region, as well as OTP data like MAC and USB IDs. But it is not a pure
>> non-volatile memory region. The data is copied into these registers by
>> the ROM at boot.
> 
> Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
> nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.

Most eFuse/OTP hardware is accessed via MMIO, not sure what that changes.

This "block" is a whole bunch of smaller logical chunks of registers,
some are actually mapped to eFuses like our MAC addresses. Regions
like factory fused MAC addresses are exactly what nvmem does well[0].

Yes, we *could* just have this whole area be one massive blanked syscon
region that every driver just manually pokes into with syscon phandles
everywhere. But that is hacky and hides details, it is not how DT normally
looks. We would like to correctly model our device now with nodes for each
"reg" region. We took the syscon shortcut before, and we want to correct
that mistake.

So what are our options? Is the objection here that this is a new nvmem
way of modeling this region changes the compatible "ti,am654-chipid"? If
so then would you be open to us adding a new compatible that uses the
nvmem nodes? We could then convert over one by one and keeping full
backwards compatibility while we do it.

Thanks,
Andrew

[0] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/nvmem/layouts/fixed-cell.yaml#L16

> 
> Best regards,
> Krzysztof
> 
> 

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 05/03/2024 15:42, Andrew Davis wrote:
> On 3/5/24 8:11 AM, Krzysztof Kozlowski wrote:
>> On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
>>> Hi Krzysztof,
>>>
>>> On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
>>>> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
>>>>> Hi,
>>>>>
>>>>> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>>>>>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>>>>>> Hi Rob,
>>>>>>>
>>>>>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>>>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>>>>>> can be a cleaner way to describe which information are used.
>>>>>>>>>
>>>>>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>>>>>> cover all required information.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>>>>>>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>>>>>>>> ---
>>>>>>>>>   .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>>>>>   1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>>>>>
>>>>>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>>>>>     reg:
>>>>>>>>>       maxItems: 1
>>>>>>>>>   
>>>>>>>>> +  nvmem-cells:
>>>>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>>>>> +
>>>>>>>>> +  nvmem-cell-names:
>>>>>>>>> +    items:
>>>>>>>>> +      - const: chipvariant
>>>>>>>>> +      - const: chippartno
>>>>>>>>> +      - const: chipmanufacturer
>>>>>>>>> +
>>>>>>>>>   required:
>>>>>>>>>     - compatible
>>>>>>>>> -  - reg
>>>>>>>>> +
>>>>>>>>> +oneOf:
>>>>>>>>> +  - required:
>>>>>>>>> +      - reg
>>>>>>>>> +  - required:
>>>>>>>>> +      - nvmem-cells
>>>>>>>>> +      - nvmem-cell-names
>>>>>>>>>   
>>>>>>>>>   additionalProperties: false
>>>>>>>>>   
>>>>>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>>>>>           compatible = "ti,am654-chipid";
>>>>>>>>>           reg = <0x43000014 0x4>;
>>>>>>>>>       };
>>>>>>>>> +  - |
>>>>>>>>> +    chipid: chipid@14 {
>>>>>>>>> +        compatible = "ti,am654-chipid";
>>>>>>>>
>>>>>>>> This isn't compatible if you have a completely different way to access
>>>>>>>> it.
>>>>>>>
>>>>>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>>>>>> Are you suggesting to use a different compatible? Or is it something
>>>>>>> else I could do to proceed with this conversion?
>>>>>>
>>>>>> What you claim now, is that you have one device with entirely different
>>>>>> interfaces and programming model. So either this is not the same device
>>>>>> or you just wrote bindings to whatever you have in driver.
>>>>>>
>>>>>> Nothing in commit msg explains this.
>>>>>>
>>>>>> What you should do? Depends. If you just write bindings for driver, then
>>>>>> stop. It's a NAK. Instead write bindings for hardware.
>>>>>>
>>>>>> If the first choice, just the hardware is somehow like this, then
>>>>>> explain in commit msg and device description, how this device can be
>>>>>> connected over other bus, not MMIO. You can draw some schematics in
>>>>>> commit msg explaining architecture etc.
>>>>>
>>>>> Sorry the information provided in the commit message is not very clear.
>>>>>
>>>>> The basic access to the registes is still MMIO. nvmem is used to have a
>>>>> better abstraction and cleaner description of the hardware.
>>>>>
>>>>> Currently most of the data is exported using the parent syscon device.
>>>>> The relevant data is read-only and contained in a single register with
>>>>> offset 0x14:
>>>>>    - Chip variant
>>>>>    - Chip part number
>>>>>    - Chip manufacturer
>>>>>
>>>>> There are more read-only registers in this section of address space.
>>>>> These are relevant to other components as they define the operating
>>>>> points for example. For the OPP table relevant are chip variant and chip
>>>>> speed (which is in a different register).
>>>>>
>>>>> Instead of devices refering to this whole register range of 0x20000 in
>>>>
>>>> Whaaaaat?
>>>>
>>>>> size, I would like to introduce this nvmem abstraction in between that
>>>>> describes the information and can directly be referenced by the devices
>>>>> that depend on it. In this case the above mentioned register with offset
>>>>> 0x14 is instead described as nvmem-layout like this:
>>>>>
>>>>> 	nvmem-layout {
>>>>> 		compatible = "fixed-layout";
>>>>> 		#address-cells = <1>;
>>>>> 		#size-cells = <1>;
>>>>>
>>>>> 		chip_manufacturer: jtagidmfg@14 {
>>>>> 			reg = <0x14 0x2>;
>>>>> 			bits = <1 11>;
>>>>> 		};
>>>>>
>>>>> 		chip_partno: jtagidpartno@15 {
>>>>> 			reg = <0x15 0x3>;
>>>>> 			bits = <4 16>;
>>>>> 		};
>>>>>
>>>>> 		chip_variant: jtagidvariant@17 {
>>>>> 			reg = <0x17 0x1>;
>>>>> 			bits = <4 4>;
>>>>> 		};
>>>>>
>>>>> 		chip_speed: jtaguseridspeed@18 {
>>>>> 			reg = <0x18 0x4>;
>>>>> 			bits = <6 5>;
>>>>> 		};
>>>>>
>>>>> The underlying registers are still the same but they are not hidden
>>>>> by the syscon phandles anymore.
>>>>>
>>>>> The device that consumes this data would now use
>>>>>
>>>>> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
>>>>> 	nvmem-cell-names = "chipvariant", "chipspeed";
>>>>>
>>>>> instead of
>>>>>
>>>>> 	syscon = <&wkup_conf>;
>>>>
>>>> syscon allows you this as well - via phandle arguments.
>>>>
>>>> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
>>>> accessing regular MMIO registers of system-controller, regardless
>>>> whether they are read-only or not (regmap handles this nicely, BTW).
>>>> Although probably Apple efuses and few others can confuse here. It still
>>>> looks like you convert regular system-controller block into nvmem,
>>>> because you prefer that Linux driver abstraction...
>>>
>>> The above mentioned data is set in the factory. There is other
>>> non-volatile data, like device feature registers, in the same address
>>> region, as well as OTP data like MAC and USB IDs. But it is not a pure
>>> non-volatile memory region. The data is copied into these registers by
>>> the ROM at boot.
>>
>> Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
>> nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.
> 
> Most eFuse/OTP hardware is accessed via MMIO, not sure what that changes.

Just check exiting NVMEM drivers, except Apple I think most if not all
are not syscon blocks.

Following such approach, each hardware block, even USB or PCI, which
exposes a read-only register with some fused value, e.g. version, should
be nvmem?

> 
> This "block" is a whole bunch of smaller logical chunks of registers,
> some are actually mapped to eFuses like our MAC addresses. Regions
> like factory fused MAC addresses are exactly what nvmem does well[0].
> 
> Yes, we *could* just have this whole area be one massive blanked syscon
> region that every driver just manually pokes into with syscon phandles
> everywhere. But that is hacky and hides details, it is not how DT normally
> looks. We would like to correctly model our device now with nodes for each
> "reg" region. We took the syscon shortcut before, and we want to correct
> that mistake.

Wait, you now mix up hardware description with Linux interface.
Describing each register as nvmem field is not a better way of
describing hardware. It is unnecessarily too granular and results in
huge and unmaintainable DTS. It is however convenient because it is nice
API for other devices. But claiming that MMIO register block is better
represented as nvmem is not correct. It is still MMIO block with
registers, like everywhere else in every other device.

> 
> So what are our options? Is the objection here that this is a new nvmem
> way of modeling this region changes the compatible "ti,am654-chipid"? If
> so then would you be open to us adding a new compatible that uses the
> nvmem nodes? We could then convert over one by one and keeping full
> backwards compatibility while we do it.

Switching from MMIO to nvmem for chipid is a different interface, so as
Rob pointed out devices are not really compatible. You claim that
devices are compatible, because there is *NO REAL NVMEM* but MMIO
wrapped in nvmem. So do you see the logic here?

Best regards,
Krzysztof


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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Andrew Davis]

On 3/5/24 11:01 AM, Krzysztof Kozlowski wrote:
> On 05/03/2024 15:42, Andrew Davis wrote:
>> On 3/5/24 8:11 AM, Krzysztof Kozlowski wrote:
>>> On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
>>>>> On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
>>>>>>> On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
>>>>>>>> Hi Rob,
>>>>>>>>
>>>>>>>> On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
>>>>>>>>> On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
>>>>>>>>>> The information k3-socinfo requires is stored in an efuse area. This
>>>>>>>>>> area is required by other devices/drivers as well, so using nvmem-cells
>>>>>>>>>> can be a cleaner way to describe which information are used.
>>>>>>>>>>
>>>>>>>>>> If nvmem-cells are supplied, the address range is not required.
>>>>>>>>>> Cells chipvariant, chippartno and chipmanufacturer are introduced to
>>>>>>>>>> cover all required information.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>>>>>>>>>> Reviewed-by: Andrew Davis <afd@ti.com>
>>>>>>>>>> ---
>>>>>>>>>>    .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>>>>>>>>>>    1 file changed, 22 insertions(+), 1 deletion(-)
>>>>>>>>>>
>>>>>>>>>> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>>> index dada28b47ea0..f085b7275b7d 100644
>>>>>>>>>> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>>> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
>>>>>>>>>> @@ -26,9 +26,24 @@ properties:
>>>>>>>>>>      reg:
>>>>>>>>>>        maxItems: 1
>>>>>>>>>>    
>>>>>>>>>> +  nvmem-cells:
>>>>>>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>>>>>>> +
>>>>>>>>>> +  nvmem-cell-names:
>>>>>>>>>> +    items:
>>>>>>>>>> +      - const: chipvariant
>>>>>>>>>> +      - const: chippartno
>>>>>>>>>> +      - const: chipmanufacturer
>>>>>>>>>> +
>>>>>>>>>>    required:
>>>>>>>>>>      - compatible
>>>>>>>>>> -  - reg
>>>>>>>>>> +
>>>>>>>>>> +oneOf:
>>>>>>>>>> +  - required:
>>>>>>>>>> +      - reg
>>>>>>>>>> +  - required:
>>>>>>>>>> +      - nvmem-cells
>>>>>>>>>> +      - nvmem-cell-names
>>>>>>>>>>    
>>>>>>>>>>    additionalProperties: false
>>>>>>>>>>    
>>>>>>>>>> @@ -38,3 +53,9 @@ examples:
>>>>>>>>>>            compatible = "ti,am654-chipid";
>>>>>>>>>>            reg = <0x43000014 0x4>;
>>>>>>>>>>        };
>>>>>>>>>> +  - |
>>>>>>>>>> +    chipid: chipid@14 {
>>>>>>>>>> +        compatible = "ti,am654-chipid";
>>>>>>>>>
>>>>>>>>> This isn't compatible if you have a completely different way to access
>>>>>>>>> it.
>>>>>>>>
>>>>>>>> Thanks, it is not entirely clear to me how I could go forward with this?
>>>>>>>> Are you suggesting to use a different compatible? Or is it something
>>>>>>>> else I could do to proceed with this conversion?
>>>>>>>
>>>>>>> What you claim now, is that you have one device with entirely different
>>>>>>> interfaces and programming model. So either this is not the same device
>>>>>>> or you just wrote bindings to whatever you have in driver.
>>>>>>>
>>>>>>> Nothing in commit msg explains this.
>>>>>>>
>>>>>>> What you should do? Depends. If you just write bindings for driver, then
>>>>>>> stop. It's a NAK. Instead write bindings for hardware.
>>>>>>>
>>>>>>> If the first choice, just the hardware is somehow like this, then
>>>>>>> explain in commit msg and device description, how this device can be
>>>>>>> connected over other bus, not MMIO. You can draw some schematics in
>>>>>>> commit msg explaining architecture etc.
>>>>>>
>>>>>> Sorry the information provided in the commit message is not very clear.
>>>>>>
>>>>>> The basic access to the registes is still MMIO. nvmem is used to have a
>>>>>> better abstraction and cleaner description of the hardware.
>>>>>>
>>>>>> Currently most of the data is exported using the parent syscon device.
>>>>>> The relevant data is read-only and contained in a single register with
>>>>>> offset 0x14:
>>>>>>     - Chip variant
>>>>>>     - Chip part number
>>>>>>     - Chip manufacturer
>>>>>>
>>>>>> There are more read-only registers in this section of address space.
>>>>>> These are relevant to other components as they define the operating
>>>>>> points for example. For the OPP table relevant are chip variant and chip
>>>>>> speed (which is in a different register).
>>>>>>
>>>>>> Instead of devices refering to this whole register range of 0x20000 in
>>>>>
>>>>> Whaaaaat?
>>>>>
>>>>>> size, I would like to introduce this nvmem abstraction in between that
>>>>>> describes the information and can directly be referenced by the devices
>>>>>> that depend on it. In this case the above mentioned register with offset
>>>>>> 0x14 is instead described as nvmem-layout like this:
>>>>>>
>>>>>> 	nvmem-layout {
>>>>>> 		compatible = "fixed-layout";
>>>>>> 		#address-cells = <1>;
>>>>>> 		#size-cells = <1>;
>>>>>>
>>>>>> 		chip_manufacturer: jtagidmfg@14 {
>>>>>> 			reg = <0x14 0x2>;
>>>>>> 			bits = <1 11>;
>>>>>> 		};
>>>>>>
>>>>>> 		chip_partno: jtagidpartno@15 {
>>>>>> 			reg = <0x15 0x3>;
>>>>>> 			bits = <4 16>;
>>>>>> 		};
>>>>>>
>>>>>> 		chip_variant: jtagidvariant@17 {
>>>>>> 			reg = <0x17 0x1>;
>>>>>> 			bits = <4 4>;
>>>>>> 		};
>>>>>>
>>>>>> 		chip_speed: jtaguseridspeed@18 {
>>>>>> 			reg = <0x18 0x4>;
>>>>>> 			bits = <6 5>;
>>>>>> 		};
>>>>>>
>>>>>> The underlying registers are still the same but they are not hidden
>>>>>> by the syscon phandles anymore.
>>>>>>
>>>>>> The device that consumes this data would now use
>>>>>>
>>>>>> 	nvmem-cells = <&chip_variant>, <&chip_speed>;
>>>>>> 	nvmem-cell-names = "chipvariant", "chipspeed";
>>>>>>
>>>>>> instead of
>>>>>>
>>>>>> 	syscon = <&wkup_conf>;
>>>>>
>>>>> syscon allows you this as well - via phandle arguments.
>>>>>
>>>>> nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
>>>>> accessing regular MMIO registers of system-controller, regardless
>>>>> whether they are read-only or not (regmap handles this nicely, BTW).
>>>>> Although probably Apple efuses and few others can confuse here. It still
>>>>> looks like you convert regular system-controller block into nvmem,
>>>>> because you prefer that Linux driver abstraction...
>>>>
>>>> The above mentioned data is set in the factory. There is other
>>>> non-volatile data, like device feature registers, in the same address
>>>> region, as well as OTP data like MAC and USB IDs. But it is not a pure
>>>> non-volatile memory region. The data is copied into these registers by
>>>> the ROM at boot.
>>>
>>> Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
>>> nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.
>>
>> Most eFuse/OTP hardware is accessed via MMIO, not sure what that changes.
> 
> Just check exiting NVMEM drivers, except Apple I think most if not all
> are not syscon blocks.
> 

We don't want it to be a syscon block either. Syscon is just another Linux
interface for accessing MMIO areas that found its way in to DT. NVMEM
is another way, which as a DT construct is more "correct" as the area
we are describing here *is* a non-volatile memory. Not a "syscon"?? whatever
that is.

> Following such approach, each hardware block, even USB or PCI, which
> exposes a read-only register with some fused value, e.g. version, should
> be nvmem?
> 

If those fused values are grouped into a region then yes, why not. Wouldn't
that be more correct to describe them as they actually are instead of
hiding them behind a "syscon" block?

>>
>> This "block" is a whole bunch of smaller logical chunks of registers,
>> some are actually mapped to eFuses like our MAC addresses. Regions
>> like factory fused MAC addresses are exactly what nvmem does well[0].
>>
>> Yes, we *could* just have this whole area be one massive blanked syscon
>> region that every driver just manually pokes into with syscon phandles
>> everywhere. But that is hacky and hides details, it is not how DT normally
>> looks. We would like to correctly model our device now with nodes for each
>> "reg" region. We took the syscon shortcut before, and we want to correct
>> that mistake.
> 
> Wait, you now mix up hardware description with Linux interface.
> Describing each register as nvmem field is not a better way of
> describing hardware. It is unnecessarily too granular and results in
> huge and unmaintainable DTS. It is however convenient because it is nice
> API for other devices. 

It is not convenient. How we have it currently as a blanket syscon node
that each driver can simply poke whatever address it wants is much easier.
We are now trying to do the more difficult (but more correct) thing here by
modeling our non-volatile memory areas as they are as nvmem nodes.

> But claiming that MMIO register block is better
> represented as nvmem is not correct. It is still MMIO block with
> registers, like everywhere else in every other device.
> 

Everything is MMIO on these SoCs, we don't have any sideband band
IO ports. Following that to its logical conclusion we should just
make the entire memory space reg = <0x0 0xffffffff> one big syscon node
then have all other driver phandle into that for their MMIO access.

>>
>> So what are our options? Is the objection here that this is a new nvmem
>> way of modeling this region changes the compatible "ti,am654-chipid"? If
>> so then would you be open to us adding a new compatible that uses the
>> nvmem nodes? We could then convert over one by one and keeping full
>> backwards compatibility while we do it.
> 
> Switching from MMIO to nvmem for chipid is a different interface, so as
> Rob pointed out devices are not really compatible. You claim that
> devices are compatible, because there is *NO REAL NVMEM* but MMIO
> wrapped in nvmem. So do you see the logic here?
> 

If the interface changing means it is not compatible then that is
fine, we would use a different compatible string to identify the
interface to be used.

This is not uncommon, the example that comes to my mind is "gpio-leds".
We used to just have named GPIO pins for our LEDs, now we can
put "gpio-leds" on top to better represent what is going on in HW.
Even though physically nothing changed, we just now have a better way
to model that HW in DT.

Andrew

> Best regards,
> Krzysztof
> 
> 

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Markus Schneider-Pargmann]

On Tue, Mar 05, 2024 at 11:41:31AM -0600, Andrew Davis wrote:
> On 3/5/24 11:01 AM, Krzysztof Kozlowski wrote:
> > On 05/03/2024 15:42, Andrew Davis wrote:
> > > On 3/5/24 8:11 AM, Krzysztof Kozlowski wrote:
> > > > On 05/03/2024 12:17, Markus Schneider-Pargmann wrote:
> > > > > Hi Krzysztof,
> > > > > 
> > > > > On Tue, Mar 05, 2024 at 08:43:03AM +0100, Krzysztof Kozlowski wrote:
> > > > > > On 04/03/2024 11:36, Markus Schneider-Pargmann wrote:
> > > > > > > Hi,
> > > > > > > 
> > > > > > > On Sat, Feb 17, 2024 at 03:25:30PM +0100, Krzysztof Kozlowski wrote:
> > > > > > > > On 14/02/2024 10:31, Markus Schneider-Pargmann wrote:
> > > > > > > > > Hi Rob,
> > > > > > > > > 
> > > > > > > > > On Tue, Feb 06, 2024 at 06:43:05PM +0000, Rob Herring wrote:
> > > > > > > > > > On Tue, Feb 06, 2024 at 03:37:09PM +0100, Markus Schneider-Pargmann wrote:
> > > > > > > > > > > The information k3-socinfo requires is stored in an efuse area. This
> > > > > > > > > > > area is required by other devices/drivers as well, so using nvmem-cells
> > > > > > > > > > > can be a cleaner way to describe which information are used.
> > > > > > > > > > > 
> > > > > > > > > > > If nvmem-cells are supplied, the address range is not required.
> > > > > > > > > > > Cells chipvariant, chippartno and chipmanufacturer are introduced to
> > > > > > > > > > > cover all required information.
> > > > > > > > > > > 
> > > > > > > > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > > > > > > > > > > Reviewed-by: Andrew Davis <afd@ti.com>
> > > > > > > > > > > ---
> > > > > > > > > > >    .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
> > > > > > > > > > >    1 file changed, 22 insertions(+), 1 deletion(-)
> > > > > > > > > > > 
> > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > > > > > > > > > > index dada28b47ea0..f085b7275b7d 100644
> > > > > > > > > > > --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > > > > > > > > > > +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> > > > > > > > > > > @@ -26,9 +26,24 @@ properties:
> > > > > > > > > > >      reg:
> > > > > > > > > > >        maxItems: 1
> > > > > > > > > > > +  nvmem-cells:
> > > > > > > > > > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > > > > > > > > +
> > > > > > > > > > > +  nvmem-cell-names:
> > > > > > > > > > > +    items:
> > > > > > > > > > > +      - const: chipvariant
> > > > > > > > > > > +      - const: chippartno
> > > > > > > > > > > +      - const: chipmanufacturer
> > > > > > > > > > > +
> > > > > > > > > > >    required:
> > > > > > > > > > >      - compatible
> > > > > > > > > > > -  - reg
> > > > > > > > > > > +
> > > > > > > > > > > +oneOf:
> > > > > > > > > > > +  - required:
> > > > > > > > > > > +      - reg
> > > > > > > > > > > +  - required:
> > > > > > > > > > > +      - nvmem-cells
> > > > > > > > > > > +      - nvmem-cell-names
> > > > > > > > > > >    additionalProperties: false
> > > > > > > > > > > @@ -38,3 +53,9 @@ examples:
> > > > > > > > > > >            compatible = "ti,am654-chipid";
> > > > > > > > > > >            reg = <0x43000014 0x4>;
> > > > > > > > > > >        };
> > > > > > > > > > > +  - |
> > > > > > > > > > > +    chipid: chipid@14 {
> > > > > > > > > > > +        compatible = "ti,am654-chipid";
> > > > > > > > > > 
> > > > > > > > > > This isn't compatible if you have a completely different way to access
> > > > > > > > > > it.
> > > > > > > > > 
> > > > > > > > > Thanks, it is not entirely clear to me how I could go forward with this?
> > > > > > > > > Are you suggesting to use a different compatible? Or is it something
> > > > > > > > > else I could do to proceed with this conversion?
> > > > > > > > 
> > > > > > > > What you claim now, is that you have one device with entirely different
> > > > > > > > interfaces and programming model. So either this is not the same device
> > > > > > > > or you just wrote bindings to whatever you have in driver.
> > > > > > > > 
> > > > > > > > Nothing in commit msg explains this.
> > > > > > > > 
> > > > > > > > What you should do? Depends. If you just write bindings for driver, then
> > > > > > > > stop. It's a NAK. Instead write bindings for hardware.
> > > > > > > > 
> > > > > > > > If the first choice, just the hardware is somehow like this, then
> > > > > > > > explain in commit msg and device description, how this device can be
> > > > > > > > connected over other bus, not MMIO. You can draw some schematics in
> > > > > > > > commit msg explaining architecture etc.
> > > > > > > 
> > > > > > > Sorry the information provided in the commit message is not very clear.
> > > > > > > 
> > > > > > > The basic access to the registes is still MMIO. nvmem is used to have a
> > > > > > > better abstraction and cleaner description of the hardware.
> > > > > > > 
> > > > > > > Currently most of the data is exported using the parent syscon device.
> > > > > > > The relevant data is read-only and contained in a single register with
> > > > > > > offset 0x14:
> > > > > > >     - Chip variant
> > > > > > >     - Chip part number
> > > > > > >     - Chip manufacturer
> > > > > > > 
> > > > > > > There are more read-only registers in this section of address space.
> > > > > > > These are relevant to other components as they define the operating
> > > > > > > points for example. For the OPP table relevant are chip variant and chip
> > > > > > > speed (which is in a different register).
> > > > > > > 
> > > > > > > Instead of devices refering to this whole register range of 0x20000 in
> > > > > > 
> > > > > > Whaaaaat?
> > > > > > 
> > > > > > > size, I would like to introduce this nvmem abstraction in between that
> > > > > > > describes the information and can directly be referenced by the devices
> > > > > > > that depend on it. In this case the above mentioned register with offset
> > > > > > > 0x14 is instead described as nvmem-layout like this:
> > > > > > > 
> > > > > > > 	nvmem-layout {
> > > > > > > 		compatible = "fixed-layout";
> > > > > > > 		#address-cells = <1>;
> > > > > > > 		#size-cells = <1>;
> > > > > > > 
> > > > > > > 		chip_manufacturer: jtagidmfg@14 {
> > > > > > > 			reg = <0x14 0x2>;
> > > > > > > 			bits = <1 11>;
> > > > > > > 		};
> > > > > > > 
> > > > > > > 		chip_partno: jtagidpartno@15 {
> > > > > > > 			reg = <0x15 0x3>;
> > > > > > > 			bits = <4 16>;
> > > > > > > 		};
> > > > > > > 
> > > > > > > 		chip_variant: jtagidvariant@17 {
> > > > > > > 			reg = <0x17 0x1>;
> > > > > > > 			bits = <4 4>;
> > > > > > > 		};
> > > > > > > 
> > > > > > > 		chip_speed: jtaguseridspeed@18 {
> > > > > > > 			reg = <0x18 0x4>;
> > > > > > > 			bits = <6 5>;
> > > > > > > 		};
> > > > > > > 
> > > > > > > The underlying registers are still the same but they are not hidden
> > > > > > > by the syscon phandles anymore.
> > > > > > > 
> > > > > > > The device that consumes this data would now use
> > > > > > > 
> > > > > > > 	nvmem-cells = <&chip_variant>, <&chip_speed>;
> > > > > > > 	nvmem-cell-names = "chipvariant", "chipspeed";
> > > > > > > 
> > > > > > > instead of
> > > > > > > 
> > > > > > > 	syscon = <&wkup_conf>;
> > > > > > 
> > > > > > syscon allows you this as well - via phandle arguments.
> > > > > > 
> > > > > > nvmem is for non-volatile memory, like OCOTP and eFUSE. This is not for
> > > > > > accessing regular MMIO registers of system-controller, regardless
> > > > > > whether they are read-only or not (regmap handles this nicely, BTW).
> > > > > > Although probably Apple efuses and few others can confuse here. It still
> > > > > > looks like you convert regular system-controller block into nvmem,
> > > > > > because you prefer that Linux driver abstraction...
> > > > > 
> > > > > The above mentioned data is set in the factory. There is other
> > > > > non-volatile data, like device feature registers, in the same address
> > > > > region, as well as OTP data like MAC and USB IDs. But it is not a pure
> > > > > non-volatile memory region. The data is copied into these registers by
> > > > > the ROM at boot.
> > > > 
> > > > Still entire block is MMIO IP in your SoC, not a efuse/OTP hardware.
> > > > nvmem is not for regular MMIO registers which are sometimes R, sometimes RW.
> > > 
> > > Most eFuse/OTP hardware is accessed via MMIO, not sure what that changes.
> > 
> > Just check exiting NVMEM drivers, except Apple I think most if not all
> > are not syscon blocks.
> > 
> 
> We don't want it to be a syscon block either. Syscon is just another Linux
> interface for accessing MMIO areas that found its way in to DT. NVMEM
> is another way, which as a DT construct is more "correct" as the area
> we are describing here *is* a non-volatile memory. Not a "syscon"?? whatever
> that is.
> 
> > Following such approach, each hardware block, even USB or PCI, which
> > exposes a read-only register with some fused value, e.g. version, should
> > be nvmem?
> > 
> 
> If those fused values are grouped into a region then yes, why not. Wouldn't
> that be more correct to describe them as they actually are instead of
> hiding them behind a "syscon" block?
> 
> > > 
> > > This "block" is a whole bunch of smaller logical chunks of registers,
> > > some are actually mapped to eFuses like our MAC addresses. Regions
> > > like factory fused MAC addresses are exactly what nvmem does well[0].
> > > 
> > > Yes, we *could* just have this whole area be one massive blanked syscon
> > > region that every driver just manually pokes into with syscon phandles
> > > everywhere. But that is hacky and hides details, it is not how DT normally
> > > looks. We would like to correctly model our device now with nodes for each
> > > "reg" region. We took the syscon shortcut before, and we want to correct
> > > that mistake.
> > 
> > Wait, you now mix up hardware description with Linux interface.
> > Describing each register as nvmem field is not a better way of
> > describing hardware. It is unnecessarily too granular and results in
> > huge and unmaintainable DTS. It is however convenient because it is nice
> > API for other devices.
> 
> It is not convenient. How we have it currently as a blanket syscon node
> that each driver can simply poke whatever address it wants is much easier.
> We are now trying to do the more difficult (but more correct) thing here by
> modeling our non-volatile memory areas as they are as nvmem nodes.
> 
> > But claiming that MMIO register block is better
> > represented as nvmem is not correct. It is still MMIO block with
> > registers, like everywhere else in every other device.
> > 
> 
> Everything is MMIO on these SoCs, we don't have any sideband band
> IO ports. Following that to its logical conclusion we should just
> make the entire memory space reg = <0x0 0xffffffff> one big syscon node
> then have all other driver phandle into that for their MMIO access.
> 
> > > 
> > > So what are our options? Is the objection here that this is a new nvmem
> > > way of modeling this region changes the compatible "ti,am654-chipid"? If
> > > so then would you be open to us adding a new compatible that uses the
> > > nvmem nodes? We could then convert over one by one and keeping full
> > > backwards compatibility while we do it.
> > 
> > Switching from MMIO to nvmem for chipid is a different interface, so as
> > Rob pointed out devices are not really compatible. You claim that
> > devices are compatible, because there is *NO REAL NVMEM* but MMIO
> > wrapped in nvmem. So do you see the logic here?
> > 
> 
> If the interface changing means it is not compatible then that is
> fine, we would use a different compatible string to identify the
> interface to be used.

So what is the acceptable approach here?

Best,
Markus

> 
> This is not uncommon, the example that comes to my mind is "gpio-leds".
> We used to just have named GPIO pins for our LEDs, now we can
> put "gpio-leds" on top to better represent what is going on in HW.
> Even though physically nothing changed, we just now have a better way
> to model that HW in DT.
> 
> Andrew
> 
> > Best regards,
> > Krzysztof
> > 
> > 

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Re: [PATCH 2/4] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells

[Krzysztof Kozlowski]

On 06/02/2024 15:37, Markus Schneider-Pargmann wrote:
> The information k3-socinfo requires is stored in an efuse area. This
> area is required by other devices/drivers as well, so using nvmem-cells
> can be a cleaner way to describe which information are used.
> 
> If nvmem-cells are supplied, the address range is not required.
> Cells chipvariant, chippartno and chipmanufacturer are introduced to
> cover all required information.
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Reviewed-by: Andrew Davis <afd@ti.com>
> ---
>  .../bindings/hwinfo/ti,k3-socinfo.yaml        | 23 ++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> index dada28b47ea0..f085b7275b7d 100644
> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> @@ -26,9 +26,24 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  nvmem-cells:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array

You do not need to redefine the type. You need constraints, so maxItems.

> +
> +  nvmem-cell-names:
> +    items:
> +      - const: chipvariant
> +      - const: chippartno
> +      - const: chipmanufacturer


Best regards,
Krzysztof


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[PATCH 3/4] soc: ti: k3-socinfo: Add support for nvmem cells

[Markus Schneider-Pargmann]

Support nvmem cells to retrieve chip variant, part number and
manufacturer. As multiple different devices depend on these information
it is cleaner to abstract efuse fields with nvmem cells.

If chipvariant nvmem cell is found, the driver assumes nvmem cells are
being used and tries to find the other fields as well. If it can't find
'chipvariant' it will try to create a regmap.

Some prints had to be updated as I don't read the full jtagid anymore.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Acked-by: Andrew Davis <afd@ti.com>
---
 drivers/soc/ti/k3-socinfo.c | 67 +++++++++++++++++++++++++------------
 1 file changed, 46 insertions(+), 21 deletions(-)

diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c
index 59101bf7cf23..99794aeb6206 100644
--- a/drivers/soc/ti/k3-socinfo.c
+++ b/drivers/soc/ti/k3-socinfo.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/mfd/syscon.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/regmap.h>
@@ -114,45 +115,68 @@ static int k3_chipinfo_probe(struct platform_device *pdev)
 	struct regmap *regmap;
 	u32 partno_id;
 	u32 variant;
-	u32 jtag_id;
 	u32 mfg;
 	int ret;
 
-	regmap = device_node_to_regmap(node);
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
-
-	ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG, &jtag_id);
-	if (ret < 0)
-		return ret;
-
-	mfg = (jtag_id & CTRLMMR_WKUP_JTAGID_MFG_MASK) >>
-	       CTRLMMR_WKUP_JTAGID_MFG_SHIFT;
+	ret = nvmem_cell_read_u32(dev, "chipvariant", &variant);
+	if (ret && ret != -ENOENT)
+		return dev_err_probe(dev, ret,
+				     "Failed to read nvmem cell 'chipvariant': %pe",
+				     ERR_PTR(ret));
+
+	if (ret != -ENOENT) {
+		ret = nvmem_cell_read_u32(dev, "chippartno", &partno_id);
+		if (ret)
+			return dev_err_probe(dev, ret,
+					     "Failed to read nvmem cell 'chippartno': %pe",
+					     ERR_PTR(ret));
+
+		ret = nvmem_cell_read_u32(dev, "chipmanufacturer", &mfg);
+		if (ret)
+			return dev_err_probe(dev, ret,
+					     "Failed to read nvmem cell 'chipmanufacturer': %pe",
+					     ERR_PTR(ret));
+	} else {
+		u32 jtag_id;
+
+		regmap = device_node_to_regmap(node);
+		if (IS_ERR(regmap))
+			return PTR_ERR(regmap);
+
+		ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG, &jtag_id);
+		if (ret < 0)
+			return ret;
+
+		mfg = (jtag_id & CTRLMMR_WKUP_JTAGID_MFG_MASK) >>
+		       CTRLMMR_WKUP_JTAGID_MFG_SHIFT;
+
+		variant = (jtag_id & CTRLMMR_WKUP_JTAGID_VARIANT_MASK) >>
+			  CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT;
+
+		partno_id = (jtag_id & CTRLMMR_WKUP_JTAGID_PARTNO_MASK) >>
+			 CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT;
+	}
 
 	if (mfg != CTRLMMR_WKUP_JTAGID_MFG_TI) {
 		dev_err(dev, "Invalid MFG SoC\n");
 		return -ENODEV;
 	}
 
-	variant = (jtag_id & CTRLMMR_WKUP_JTAGID_VARIANT_MASK) >>
-		  CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT;
-
-	partno_id = (jtag_id & CTRLMMR_WKUP_JTAGID_PARTNO_MASK) >>
-		 CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT;
-
 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 	if (!soc_dev_attr)
 		return -ENOMEM;
 
 	ret = k3_chipinfo_partno_to_names(partno_id, soc_dev_attr);
 	if (ret) {
-		dev_err(dev, "Unknown SoC JTAGID[0x%08X]: %d\n", jtag_id, ret);
+		dev_err(dev, "Unknown SoC JTAGID[variant=0x%X, partno=0x%X]: %d\n",
+			variant, partno_id, ret);
 		goto err;
 	}
 
 	ret = k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr);
 	if (ret) {
-		dev_err(dev, "Unknown SoC SR[0x%08X]: %d\n", jtag_id, ret);
+		dev_err(dev, "Unknown SoC SR[variant=0x%X, partno=0x%X]: %d\n",
+			variant, partno_id, ret);
 		goto err;
 	}
 
@@ -166,9 +190,10 @@ static int k3_chipinfo_probe(struct platform_device *pdev)
 		goto err_free_rev;
 	}
 
-	dev_info(dev, "Family:%s rev:%s JTAGID[0x%08x] Detected\n",
+	dev_info(dev, "Family:%s rev:%s JTAGID[variant=0x%X, partno=0x%X] Detected\n",
 		 soc_dev_attr->family,
-		 soc_dev_attr->revision, jtag_id);
+		 soc_dev_attr->revision,
+		 variant, partno_id);
 
 	return 0;
 
-- 
2.43.0


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[PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes

[Markus Schneider-Pargmann]

Add efuse nodes describing chip variant and speed grade.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
---
 arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index fef76f52a52e..14419df43624 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -14,10 +14,44 @@ wkup_conf: syscon@43000000 {
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x43000000 0x20000>;
 
+		wkup_efuse: efuse@0 {
+			compatible = "socionext,uniphier-efuse";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x0 0x200>;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				chip_manufacturer: jtagidmfg@14 {
+					reg = <0x14 0x2>;
+					bits = <1 11>;
+				};
+
+				chip_partno: jtagidpartno@15 {
+					reg = <0x15 0x3>;
+					bits = <4 16>;
+				};
+
+				chip_variant: jtagidvariant@17 {
+					reg = <0x17 0x1>;
+					bits = <4 4>;
+				};
+
+				chip_speed: jtaguseridspeed@18 {
+					reg = <0x18 0x4>;
+					bits = <6 5>;
+				};
+			};
+		};
+
 		chipid: chipid@14 {
 			bootph-all;
 			compatible = "ti,am654-chipid";
-			reg = <0x14 0x4>;
+			nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
+			nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
 		};
 	};
 
-- 
2.43.0


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Re: [PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes

[Andrew Davis]

On 2/6/24 8:37 AM, Markus Schneider-Pargmann wrote:
> Add efuse nodes describing chip variant and speed grade.
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++++++++++++++-
>   1 file changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> index fef76f52a52e..14419df43624 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> @@ -14,10 +14,44 @@ wkup_conf: syscon@43000000 {
>   		#size-cells = <1>;
>   		ranges = <0x0 0x00 0x43000000 0x20000>;
>   
> +		wkup_efuse: efuse@0 {
> +			compatible = "socionext,uniphier-efuse";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x0 0x200>;
> +
> +			nvmem-layout {
> +				compatible = "fixed-layout";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				chip_manufacturer: jtagidmfg@14 {
> +					reg = <0x14 0x2>;
> +					bits = <1 11>;
> +				};
> +
> +				chip_partno: jtagidpartno@15 {
> +					reg = <0x15 0x3>;
> +					bits = <4 16>;
> +				};
> +
> +				chip_variant: jtagidvariant@17 {
> +					reg = <0x17 0x1>;
> +					bits = <4 4>;
> +				};
> +
> +				chip_speed: jtaguseridspeed@18 {
> +					reg = <0x18 0x4>;
> +					bits = <6 5>;
> +				};
> +			};
> +		};
> +
>   		chipid: chipid@14 {

If you remove the reg property you will want to drop the @14
also or you will get a DT check warning. That needs fixed
in the binding example too (and the binding nodename pattern).

Andrew

>   			bootph-all;
>   			compatible = "ti,am654-chipid";
> -			reg = <0x14 0x4>;
> +			nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>;
> +			nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer";
>   		};
>   	};
>   

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