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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id d9-20020a056830138900b006e13c3274c2sm580143otq.8.2024.02.08.07.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 07:35:33 -0800 (PST) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1rY6R2-00EsNe-EW; Thu, 08 Feb 2024 11:35:32 -0400 Date: Thu, 8 Feb 2024 11:35:32 -0400 From: Jason Gunthorpe To: Shameer Kolothum Cc: kvmarm@lists.linux.dev, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, kevin.tian@intel.com, alex.williamson@redhat.com, maz@kernel.org, oliver.upton@linux.dev, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, jonathan.cameron@huawei.com Subject: Re: [RFC PATCH v2 0/7] iommu/arm-smmu-v3: Use pinned KVM VMID for stage 2 Message-ID: <20240208153532.GO31743@ziepe.ca> References: <20240208151837.35068-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240208151837.35068-1-shameerali.kolothum.thodi@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240208_073535_903760_68B6D66D X-CRM114-Status: GOOD ( 20.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 08, 2024 at 03:18:30PM +0000, Shameer Kolothum wrote: > Hi, > > On an ARM64 system with a SMMUv3 implementation that fully supports > Broadcast TLB Maintenance(BTM) feature as part of the Distributed > Virtual Memory(DVM) protocol, the CPU TLB invalidate instructions are > received by SMMUv3. This is very useful when the SMMUv3 shares the > page tables with the CPU(eg: Guest SVA use case). For this to work, > the SMMUv3 must use the same VMID that is allocated by KVM to configure > the nested stage 2(S2) translations. Ah so you are going all the way and looking to enable BTM within a vSVA environment too? > An earlier proposal sent out[1] a while back resulted in changing the > ARM64/KVM VMID allocator similar to the ASID allocator to make it > better suited for this. > > This RFC adds, > -Support for pinned KVM VMID. > -Support associating KVM pointer and iommufd ctx. > -Changes to domain_alloc_user() to receive a kvm pointer. > -Configure SMMUV3 S2 using KVM VMID > -Finally enable BTM only if SMMUV3 supports S1 translation. This > is to make sure that PAGING domains always use S1 and S2 is only > used for nested domains with a valid KVM. The idea is to make sure > when BTM is enabled in Guest, we use KVM VMID for S2. > > Not sure I miss any explicit TLB invalidations with any use case > that may configure a S2 with a private VMID that matches a KVM > one. > > This is based on Jason's ongoing SMMUv3 refactor series[2]. I'm glad to see this, thank you for finishing the BTM stuff! If someone is using it I wonder if we need to get a more solid answer on the races with invalidation an ASID reassign.. I added some notes in comments in part 2 after I audited all of it. Jason _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel