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From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org,
	krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org,
	conor+dt@kernel.org
Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, andre.draszik@linaro.org,
	peter.griffin@linaro.org, kernel-team@android.com,
	willmcvicker@google.com, devicetree@vger.kernel.org,
	Tudor Ambarus <tudor.ambarus@linaro.org>
Subject: [PATCH v3 12/12] spi: s3c64xx: switch exynos850 to new port config data
Date: Fri, 16 Feb 2024 07:05:55 +0000	[thread overview]
Message-ID: <20240216070555.2483977-13-tudor.ambarus@linaro.org> (raw)
In-Reply-To: <20240216070555.2483977-1-tudor.ambarus@linaro.org>

Exynos850 has the same version of USI SPI (v2.1) as GS101.
Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port
config data.

Backward compatibility with DT is not broken because when alises are
set:
- the SPI core will set the bus number according to the alias ID
- the FIFO depth is always the same size for exynos850 (64 bytes) no
  matter the alias ID number.

Advantages of the change:
- drop dependency on the OF alias ID.
- FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI
  IPs, all with 64 bytes FIFO depths.
- use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial
  masks is misleading and can hide problems of the driver logic.

Just compiled tested.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 drivers/spi/spi-s3c64xx.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 784786407d2e..9fcbe040cb2f 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
 };
 
 static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
-	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
-	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f },
-	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
-	.rx_lvl_offset	= 15,
+	.fifo_depth	= 64,
+	.rx_fifomask	= S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
+	.tx_fifomask	= S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
 	.tx_st_done	= 25,
 	.clk_div	= 4,
 	.high_speed	= true,
-- 
2.44.0.rc0.258.g7320e95886-goog


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  parent reply	other threads:[~2024-02-16  7:06 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-16  7:05 [PATCH v3 00/12] spi: s3c64xx: remove OF alias ID dependency Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 01/12] spi: dt-bindings: introduce FIFO depth properties Tudor Ambarus
2024-02-16 19:45   ` Conor Dooley
2024-02-16  7:05 ` [PATCH v3 02/12] spi: s3c64xx: define a magic value Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 03/12] spi: s3c64xx: allow full FIFO masks Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 04/12] spi: s3c64xx: determine the fifo depth only once Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 07/12] spi: s3c64xx: let the SPI core determine the bus number Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Tudor Ambarus
2024-02-16  7:05 ` [PATCH v3 11/12] spi: s3c64xx: switch gs101 to new port config data Tudor Ambarus
2024-02-16  7:05 ` Tudor Ambarus [this message]
2024-02-21 17:56   ` [PATCH v3 12/12] spi: s3c64xx: switch exynos850 " Tudor Ambarus
2024-02-24 23:59     ` Sam Protsenko
2024-03-06 14:08 ` [PATCH v3 00/12] spi: s3c64xx: remove OF alias ID dependency Mark Brown

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