From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95330C5475B for ; Tue, 20 Feb 2024 15:16:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CClBTzXmN9AjC6QBNn8SCsRD0A4vkn1hSd7tvfNslTc=; b=dHWPexD1TrUdCg CLIh+fa30BnGlkmQqbyE8dTiqbUsDmAK+hII2SjAH9NYqaLDBXybZz+NYaOPJNKErIU8Dg9IY1qVu EVFAAu35ATuhZ1HRal1VJR3Cs6XROZX7c89tlsTGdvPavZOieo1j4+VKh/GLO0CJUBNHEKhNRAFF0 TYQFNHU18215SYLfPRsY4kMuT7IenCf8nB7AUtBTaKHcUVBCfKv+P5G8DJoTYyCD9mA0XKzr/GHi9 nCc4p3BsiyKgUEP9398EDyQxxSQxH/mc4vKEvWOv54rBnxlUlxOrqAYYi7O20ycK5pzDbYZicoWqm DALqvULyu52GdPeHizpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcRqu-0000000FE63-30oD; Tue, 20 Feb 2024 15:16:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcRqr-0000000FE4m-1Zog for linux-arm-kernel@lists.infradead.org; Tue, 20 Feb 2024 15:16:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 008E4FEC; Tue, 20 Feb 2024 07:16:43 -0800 (PST) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A34E53F73F; Tue, 20 Feb 2024 07:16:02 -0800 (PST) Date: Tue, 20 Feb 2024 15:16:00 +0000 From: Joey Gouly To: Marc Zyngier Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon , Catalin Marinas Subject: Re: [PATCH 04/13] KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2 Message-ID: <20240220151600.GC8575@e124191.cambridge.arm.com> References: <20240219092014.783809-1-maz@kernel.org> <20240219092014.783809-5-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240219092014.783809-5-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240220_071609_547528_BB091A8F X-CRM114-Status: GOOD ( 26.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Mon, Feb 19, 2024 at 09:20:05AM +0000, Marc Zyngier wrote: > Add the HCR_EL2 configuration for FEAT_NV2, adding the required > bits for running a guest hypervisor, and overall merging the > allowed bits provided by the guest. > > This heavily replies on unavaliable features being sanitised > when the HCR_EL2 shadow register is accessed, and only a couple > of bits must be explicitly disabled. > > Non-NV guests are completely unaffected by any of this. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kvm/hyp/include/hyp/switch.h | 4 +-- > arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- > arch/arm64/kvm/hyp/vhe/switch.c | 34 ++++++++++++++++++++++++- > 4 files changed, 36 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 9e8999592f3a..a5361d9032a4 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -498,6 +498,7 @@ > #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) > #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > +#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) > > #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) I'm seeing double! (SYS_VNCR_EL2 is already defined a few lines down) > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h > index e3fcf8c4d5b4..f5f701f309a9 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > @@ -271,10 +271,8 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) > __deactivate_traps_hfgxtr(vcpu); > } > > -static inline void ___activate_traps(struct kvm_vcpu *vcpu) > +static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr) > { > - u64 hcr = vcpu->arch.hcr_el2; > - > if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM)) > hcr |= HCR_TVM; > > diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c > index c50f8459e4fc..4103625e46c5 100644 > --- a/arch/arm64/kvm/hyp/nvhe/switch.c > +++ b/arch/arm64/kvm/hyp/nvhe/switch.c > @@ -40,7 +40,7 @@ static void __activate_traps(struct kvm_vcpu *vcpu) > { > u64 val; > > - ___activate_traps(vcpu); > + ___activate_traps(vcpu, vcpu->arch.hcr_el2); > __activate_traps_common(vcpu); > > val = vcpu->arch.cptr_el2; > diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c > index 58415783fd53..29f59c374f7a 100644 > --- a/arch/arm64/kvm/hyp/vhe/switch.c > +++ b/arch/arm64/kvm/hyp/vhe/switch.c > @@ -33,11 +33,43 @@ DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); > DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); > DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); > > +/* > + * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1 > + * semantics, irrespective of the configuration), but that cannot be > + * applied to the actual HW as things would otherwise break badly. > + * > + * - TGE: we want to use EL1, which is incompatible with it being set Can you make this a bit clearer: we want the guest to use EL1 Assuming I've understood correctly. I first read it as 'we' == kvm. > + * > + * - API/APK: for hysterical raisins, we enable PAuth lazily, which > + * means that the guest's bits cannot be directly applied (we really > + * want to see the traps). Revisit this at some point. > + */ > +#define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK) > + > +static u64 __compute_hcr(struct kvm_vcpu *vcpu) > +{ > + u64 hcr = vcpu->arch.hcr_el2; > + > + if (!vcpu_has_nv(vcpu)) > + return hcr; > + > + if (is_hyp_ctxt(vcpu)) { > + hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB; > + > + if (!vcpu_el2_e2h_is_set(vcpu)) > + hcr |= HCR_NV1; > + > + write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2); > + } > + > + return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE); > +} > + > static void __activate_traps(struct kvm_vcpu *vcpu) > { > u64 val; > > - ___activate_traps(vcpu); > + ___activate_traps(vcpu, __compute_hcr(vcpu)); > > if (has_cntpoff()) { > struct timer_map map; Otherwise, Reviewed-by: Joey Gouly Thanks, Joey _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel