From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D14BC48BC3 for ; Wed, 21 Feb 2024 16:09:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UA+jZRQsvbpULJ42EgKEp5oY67ZbbijG7T5VwXj4CEE=; b=nUUsvOsLItdFfM SWFZE5hx2Sp0zYlEU1nyPhjrgil+TEp3AB/TcQAZLpDHGl48fonXaJmPIc+yCJ/DZm7YB8LqgrBVc 6vApW83+dDtHDStnkB+GR9W+uWuQrXCNDGTPAACJ2okOuYGR1jH92HockLaZ1xWNA0c7mnS/tX7ll 7PDKDcgXixNxCfiYl0xqL3Ik0UzyOUxu5EvPsJqMXnl7DqUkrU586rehpWJhHjw1esVfmlIsJIphQ wpEIk7RfgXfOucAgkDMr0fnm+ASmjgXBzuEFLMeVlFCRKykmxVAcRHgNrn/kCDXs1HD3yZBMAyvrh aEWtI7TE2hSnzvdUhMCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcp9X-00000001ecd-0LeP; Wed, 21 Feb 2024 16:08:59 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcp9U-00000001ebA-15EX for linux-arm-kernel@lists.infradead.org; Wed, 21 Feb 2024 16:08:57 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id B21EC61305; Wed, 21 Feb 2024 16:08:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91373C433F1; Wed, 21 Feb 2024 16:08:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708531735; bh=65OECqX9KxYAQydC9rm3J5R8qN/iq04mlYabKZdFS5I=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=HztFuJxseaQk0aYkeyC7H7JT1tB8CxESXcerSlvmnFx+KJKuYku4PjG3rzuYuv5MS MHXznbwvVe1NKXst5Wr63JMcZEBYmHTm32SM/eF3avlfczRZKJ4RG5RN9yv/mTH47d /bsQS9JfHR5yiPndbtTYqvl5zKkCz6GRm5bn16K4JZU03tfOaoHoHC29i9kiSs/2F2 ndM8ukJ5RLlTdp78vxD+E6pQ6x0MdNLqvqNU6goGHySWyxwxDcIxcXnYoS3PZymCt7 DpMUJBMFkPUzNky8TA5IZ91yqyTG+t+5PofaFWh58ItJKV0yV/PePTQq6ii07Q/l4N bl03CPNN8bziQ== Date: Wed, 21 Feb 2024 16:08:50 +0000 From: Will Deacon To: "ni.liqiang" Cc: danielmentz@google.com, iommu@lists.linux.dev, jin.qi@zte.com.cn, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robin.murphy@arm.com, ni.liqiang@zte.com.cn Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization. Message-ID: <20240221160849.GB7362@willie-the-truck> References: <20240219091709.GA4105@willie-the-truck> <20240221152629.3656-1-niliqiang.io@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240221152629.3656-1-niliqiang.io@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240221_080856_407205_27C8F31B X-CRM114-Status: GOOD ( 29.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 21, 2024 at 11:26:29PM +0800, ni.liqiang wrote: > >> The SMMU registers are accessed using Device-nGnRE attributes. It is > >> my understanding that, for Device-nGnRE, the Arm architecture requires > >> that writes to the same peripheral arrive at the endpoint in program > >> order. > > > > Yup, that's correct. The "nR" part means "non-Reordering", so something > > else is going on here. > > Yes, the SMMU registers are accessed using Device-nGnRE attributes. > > One additional point to note is: in cases where there is a failure writing > to the CMDQ base address register, the testing environment was a > multi-die, multi-socket server. This issue has not been observed on a > single-die server. I apologize for omitting this information in my initial > patch submission. Uh-oh, smells like a hardware issue ;p I wonder if Device-nGnRnE behaves any differently? > Over the past few days, I have referenced the kernel source code and > ported the SMMU register initialization process. Through multiple stress > tests, I have attempted to reproduce the CMDQ base address register write > failure issue. The summarized results of my experiments are as follows: > 1. When testing with one CPU core bound using taskset, the initialization > process was executed 300,000 times without encountering the CMDQ base > address register write failure issue. However, when not binding CPU using > taskset, the issue was reproduced around 1,000 iterations into the test. > 2. Without CPU binding, I inserted a memory barrier between accesses to > the CMDQ_BASE register and CMDQEN register, similar to the modification > made in the patch. After executing the initialization process 300,000 > times, the CMDQ base address register write failure issue did not occur. > > Based on these observations and joint analysis with CMN colleagues, we > speculate that in the SMMU register initialization process, if the CPU > core changes, and these CPUs are located on different dies, the underlying > 4 CCG ports are utilized to perform die-to-die accesses. However, in our > current strategy, these 4 CCG ports cannot guarantee ordering, resulting > in the completion of CMDQEN writing before the completion of CMDQ base > address writing. (Disclaimer: I don't know what a CCG port is) Hmmm. The part that doesn't make sense to me here is that migrating between CPUs implies context-switching, and we have a DSB on that path in __switch_to(). So why would adding barriers to the driver help? Maybe it just changes the timing? > From the analysis above, it seems that modifying the die-to-die access > strategy to achieve ordering of Device-nGnRE memory might be a better > solution compared to adding a memory barrier? I'm not sure what you're proposing, but I don't think Linux should be changed to accomodate this. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel