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From: "ni.liqiang" <ni_liqiang@126.com>
To: will@kernel.org, danielmentz@google.com
Cc: iommu@lists.linux.dev, jin.qi@zte.com.cn, joro@8bytes.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, ni.liqiang@zte.com.cn,
	niliqiang.io@gmail.com, robin.murphy@arm.com
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.
Date: Sat, 24 Feb 2024 00:20:10 +0800	[thread overview]
Message-ID: <20240223162010.6884-1-ni_liqiang@126.com> (raw)
In-Reply-To: <20240221160849.GB7362@willie-the-truck>

> (Disclaimer: I don't know what a CCG port is)

CCG(CXL Gateway) is a part of the CMN700 Coherent Mesh Network. It plays
a crucial role in facilitating cross-die access in a multi-chip system.

> Hmmm. The part that doesn't make sense to me here is that migrating between
> CPUs implies context-switching, and we have a DSB on that path in
> __switch_to(). So why would adding barriers to the driver help? Maybe it
> just changes the timing?

This is very likely. Through our experiments, adding a delay before CMDQEN
does not reproduce the failure of writing to the CMDQ base register.

> I'm not sure what you're proposing, but I don't think Linux should be
> changed to accomodate this.

I am very grateful for the responses from both of you experts. We will
continue to check the current hardware configuration of the system
and attempt to fix this issue.
Once again, I express my thanks. Thank you.


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      reply	other threads:[~2024-02-23 16:21 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-18  5:02 [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization ni.liqiang
2024-02-19  5:44 ` Daniel Mentz
2024-02-19  9:17   ` Will Deacon
2024-02-21 15:26     ` ni.liqiang
2024-02-21 16:08       ` Will Deacon
2024-02-23 16:20         ` ni.liqiang [this message]

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