Re: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver

claudiu beznea
2024-03-18T20:18:04Z

On 18.03.2024 11:25, Varshini.Rajendran@microchip.com wrote:
> Hi Claudiu,
>
> On 11/03/24 11:28 am, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 23.02.2024 19:28, Varshini Rajendran wrote:
>>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>> Changes in v4:
>>> - Changed variable name alloc_mem to clk_mux_buffer to be more
>>> suggestive
>>> - Changed description of @f structure member appropriately
>>> ---
>>> drivers/clk/at91/Makefile | 1 +
>>> drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 947 insertions(+)
>>> create mode 100644 drivers/clk/at91/sam9x7.c
>>>
>>> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
>>> index 89061b85e7d2..8e3684ba2c74 100644
>>> --- a/drivers/clk/at91/Makefile
>>> +++ b/drivers/clk/at91/Makefile
[ ... ]

>>> +static const struct {
>>> + const char *n;
>>> + const char *p;
>>> + const struct clk_pll_layout *l;
>>> + u8 t;
>>> + const struct clk_pll_characteristics *c;
>>> + unsigned long f;
>>> + u8 eid;
>>> +} sam9x7_plls[][PLL_ID_MAX] = {
>>> + [PLL_ID_PLLA] = {
>>> + {
>>> + .n = "plla_fracck",
>>> + .p = "mainck",
>>> + .l = &plla_frac_layout,
>>> + .t = PLL_TYPE_FRAC,
>>> + /*
>>> + * This feeds plla_divpmcck which feeds CPU. It should
>>> + * not be disabled.
>>> + */
>>> + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>>> + .c = &plla_characteristics,
>>> + },
>>> +
>>> + {
>>> + .n = "plla_divpmcck",
>>> + .p = "plla_fracck",
>>> + .l = &pll_divpmc_layout,
>>
>> You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW
>> PLL freq dividers" that this has div2 but it is registered w/ a layout that
>> has .div2 = 0.
>
> This is handled in the above plla_fracck fractional part as defined in
> the plla_frac_layout.

Ah, right. I missed the changes in sam9x60_frac_pll_recalc_rate().