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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 27, 2024 at 12:47:13PM +0000, Will Deacon wrote: > On Mon, Feb 26, 2024 at 01:07:12PM -0400, Jason Gunthorpe wrote: > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 0ffb1cf17e0b2e..9805d989dafd79 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -48,6 +48,9 @@ enum arm_smmu_msi_index { > > ARM_SMMU_MAX_MSIS, > > }; > > > > +static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, > > + ioasid_t sid); > > + > > static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { > > [EVTQ_MSI_INDEX] = { > > ARM_SMMU_EVTQ_IRQ_CFG0, > > @@ -971,6 +974,199 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) > > arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); > > } > > > > +/* > > + * Based on the value of ent report which bits of the STE the HW will access. It > > + * would be nice if this was complete according to the spec, but minimally it > > + * has to capture the bits this driver uses. > > + */ > > +static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent, > > + struct arm_smmu_ste *used_bits) > > +{ > > + unsigned int cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent->data[0])); > > + > > + used_bits->data[0] = cpu_to_le64(STRTAB_STE_0_V); > > + if (!(ent->data[0] & cpu_to_le64(STRTAB_STE_0_V))) > > + return; > > + > > + used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_CFG); > > + > > + /* S1 translates */ > > + if (cfg & BIT(0)) { > > + used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_S1FMT | > > + STRTAB_STE_0_S1CTXPTR_MASK | > > + STRTAB_STE_0_S1CDMAX); > > + used_bits->data[1] |= > > + cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | > > + STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | > > + STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | > > + STRTAB_STE_1_EATS); > > + used_bits->data[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID); > > + } > > + > > + /* S2 translates */ > > + if (cfg & BIT(1)) { > > + used_bits->data[1] |= > > + cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_SHCFG); > > + used_bits->data[2] |= > > + cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | > > + STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | > > + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R); > > + used_bits->data[3] |= cpu_to_le64(STRTAB_STE_3_S2TTB_MASK); > > + } > > + > > + if (cfg == STRTAB_STE_0_CFG_BYPASS) > > + used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); > > +} > > I think this looks much nicer now that we've ironed out SHCFG, but I don't > understand why you've dropped it from the used_bits array for the > S1DSS=BYPASS case. It's still needed there, right? Ultimately yes, however at this moment S1DSS is not used by the driver, so it is not needed in this patch. Previously I included it under the idea of making this logic complete from the start, but due to the other requests to move stuff closer to when it is first needed I shifted the S1DSS check into the patch in part 2 that actually adds it to the driver. It looks like this: used_bits[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID); /* * See 13.5 Summary of attribute/permission configuration fields * for the SHCFG behavior. */ if (FIELD_GET(STRTAB_STE_1_S1DSS, le64_to_cpu(ent[1])) == STRTAB_STE_1_S1DSS_BYPASS) used_bits[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); Let me know which way you prefer. Jason _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel