From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3ED0C54E60 for ; Thu, 14 Mar 2024 13:50:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wTy9CBvQGDJSDpg1BGle3uLLmC3KgRHG1metOvkBCGo=; b=FUQsmsEB/zEGjC nTZrd1z8USe42QyFq0fbcFGYHwslHtC8Yi3CcBvUvf9wCSX4uOhTYQOfEPG/D31RFWA8wdXnlMHmc WkTs6uYhjONuihhAn4ze6Iqw+xP82K2nbedAfL/Ac0OsoEwHkeURXoL/Xt5E7a9OKqxjb5doHbJ12 U7rF7o+A4f9TJCPvShnnwbMMOVN4TGQBQYWlkDQnuOsBLmXhvWO4v0VmMsqvlDtSFNMOQn4qZ7QjC 4wAy35cQFs5cUvpCIc2lH2blz4yIVRbivf3ZZDZEeqfOYUZ/vKz3tUG0lclURbJA0DpCy6vyztn13 /VmCfO5vuTo4rGloDLhg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rklSu-0000000EUI6-3Drf; Thu, 14 Mar 2024 13:49:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rklSr-0000000EUET-287M for linux-arm-kernel@lists.infradead.org; Thu, 14 Mar 2024 13:49:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8FFD1007; Thu, 14 Mar 2024 06:50:17 -0700 (PDT) Received: from e130802.arm.com (e130802.arm.com [10.1.33.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB2483F762; Thu, 14 Mar 2024 06:49:37 -0700 (PDT) Date: Thu, 14 Mar 2024 13:49:28 +0000 From: Abdellatif El Khlifi To: Robin Murphy Cc: Bjorn Andersson , Mathieu Poirier , Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Krzysztof Kozlowski , Conor Dooley , Drew.Reed@arm.com, Adam.Johnston@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: Re: [PATCH 3/3] dt-bindings: remoteproc: Add Arm remoteproc Message-ID: <20240314134928.GA27077@e130802.arm.com> References: <20240301164227.339208-1-abdellatif.elkhlifi@arm.com> <20240301164227.339208-4-abdellatif.elkhlifi@arm.com> <8c784016-9257-4d8a-b956-a0a406746c76@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8c784016-9257-4d8a-b956-a0a406746c76@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_064945_716170_44CE3B8D X-CRM114-Status: GOOD ( 27.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Robin, > > + firmware-name: > > + description: | > > + Default name of the firmware to load to the remote processor. > > So... is loading the firmware image achieved by somehow bitbanging it > through the one reset register, maybe? I find it hard to believe this is a > complete and functional binding. > > Frankly at the moment I'd be inclined to say it isn't even a remoteproc > binding (or driver) at all, it's a reset controller. Bindings are a contract > for describing the hardware, not the current state of Linux driver support - > if this thing still needs mailboxes, shared memory, a reset vector register, > or whatever else to actually be useful, those should be in the binding from > day 1 so that a) people can write and deploy correct DTs now, such that > functionality becomes available on their systems as soon as driver support > catches up, and b) the community has any hope of being able to review > whether the binding is appropriately designed and specified for the purpose > it intends to serve. This is an initial patchset for allowing to turn on and off the remote processor. The FW is already loaded before the Corstone-1000 SoC is powered on and this is done through the FPGA board bootloader in case of the FPGA target. Or by the Corstone-1000 FVP model (emulator). The plan for the driver is as follows: Step 1: provide a foundation driver capable of turning the core on/off Step 2: provide mailbox support for comms Step 3: provide FW reload capability Steps 2 & 3 are waiting for a HW update so the Cortex-A35 (running Linux) can share memory with the remote core. So, when memory sharing becomes available in the FPGA and FVP the DT binding will be upgraded with: - mboxes property specifying the RX/TX mailboxes (based on MHU v2) - memory-region property describing the virtio vrings Currently the mailbox controller does exist in the HW but is not usable via virtio (no memory sharing available). Do you recommend I add the mboxes property even currently we can't do the comms ? > For instance right now it seems somewhat tenuous to describe two consecutive > 32-bit registers as separate "reg" entries, but *maybe* it's OK if that's > all there ever is. However if it's actually going to end up needing several > more additional MMIO and/or memory regions for other functionality, then > describing each register and location individually is liable to get > unmanageable really fast, and a higher-level functional grouping (e.g. these > reset-related registers together as a single 8-byte region) would likely be > a better design. Currently the HW provides only 2 registers to control the remote processors: The reset control and status registers. It makes sense to me to use a mapped region of 8 bytes for both registers rather than individual registers (since they are consecutive). I'll update that, thanks for the suggestion. Abdellatif, Cheers _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel