From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 797D3C6FD1F for ; Fri, 29 Mar 2024 12:48:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DfCcBebIEOS4zQEyw+/LOoAeCaDaC7KGocjI1iP4dSg=; b=Chr5YZG8srx/+p d6XH7QD4Ka8PhuuiKvYpuR0UWiXd/Kqnt5HrenD4gNOfWgkQYiARQtrxFLi62gl7VH69CITzbWaFz JjnqL2zcSq/F7EEKqWYtkBelmeiipEorNKx5NV+5eZ56mKFxxccTShLf46jSRuzWWPFSNeRsyTZv8 2o+sZMhP192Mu9QAXr6EkAmzou5lU5/8RtiKmcJZk6ttRyEJ0qYlS4kShBaRk8bkQybcm9D3WA8iE bWpYbGEkZXjPmcJbXLtBqgit4fOkU3sj1bHO26fOr0j2w8WDeCI5Rvhh2jeAUmIhYesZbU6qVVTIe QJuInQ4ebZ72Bk6dg1aA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqBeJ-00000000SzJ-3x4f; Fri, 29 Mar 2024 12:48:00 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqBbn-00000000RjP-0AiC for linux-arm-kernel@bombadil.infradead.org; Fri, 29 Mar 2024 12:45:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=wvtV7+dxDjurcd31HIu5NPC0dn+9v0MAS7xThi/e9W0=; b=HZUxmgJenNIYjNggvP4R/Wq9Fh or2a5l1v1S85Q7VZUt9SbV9Aax+PjocZ563CPLvq/PwAV+9zkCmtnSwR2+86XN3huQuIemVXVZ4+p qwHE7XnvGWeVC8iY+akLC58bcBznk5l53Hv3O4iwotQrI0q29OxVfGmlTxd9ATuS3RvD06S/W5+xh tKWNRz3Dw+9rdxvkw2gmE8Nu0RBfTzwn2Eu3g22xQWme1soUEW5+sqzpmy6taTUDaOfSZA2uoNc+e NjDXK0GFZ+WM41AhHNaTqaJC17MFp/QGxptPuFWyiMxzPe4jPikz5pQP+oyeCYR0sPaqUDx3Ug9MH /2UrU9dw==; Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rqBbj-00000001ZPj-2k7J for linux-arm-kernel@lists.infradead.org; Fri, 29 Mar 2024 12:45:21 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 7D2A361931; Fri, 29 Mar 2024 12:45:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FC9EC433C7; Fri, 29 Mar 2024 12:45:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711716318; bh=D5Ui/gp8sF9f1UzEJQ3vaUwkLLb4ponSFyCgCJx7zIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TqpzFu03QBArd6hbAOhqcxn48noWw8dQ6XsN7Cq+MHhMHx5+AfRvRMNUGi1MgRL83 LWNrpsosOzRS6fENJKMU5zQ60tPwNnunSc2iZhGBpdFHjQt8q1jnSaqF6TUHkAz/Vi RMGggrbu6sCrPBsJwDt/Ovbg0f2n8mVMuqv2ENzvA+EhfyF+V5wPodI3R+WmXPNs3o HHmUkgRylexQcM82Hy1f5Sq8uG8zpnkt1OsFcRt9sOAQYTWTJT7cO4a39GJT95dSMo tgyJqBkb+mVOIiAYnszNjNGm7ysaq7FTU9vwwRP3YErBTQWDL72xQdtJ6rN7oeIKzs EyYcaS9Zz2szg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Junhao He , Yicong Yang , Will Deacon , Sasha Levin , jonathan.cameron@huawei.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 59/75] drivers/perf: hisi: Enable HiSilicon Erratum 162700402 quirk for HIP09 Date: Fri, 29 Mar 2024 08:42:40 -0400 Message-ID: <20240329124330.3089520-59-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329124330.3089520-1-sashal@kernel.org> References: <20240329124330.3089520-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.23 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_124519_974358_8FDF37F7 X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Junhao He [ Upstream commit e10b6976f6b9afdf3564f88c851e42d139bb19c0 ] HiSilicon UC PMU v2 suffers the erratum 162700402 that the PMU counter cannot be set due to the lack of clock under power saving mode. This will lead to error or inaccurate counts. The clock can be enabled by the PMU global enabling control. This patch tries to fix this by set the UC PMU enable before set event period to turn on the clock, and then restore the UC PMU configuration. The counter register can hold its value without a clock. Signed-off-by: Junhao He Reviewed-by: Yicong Yang Link: https://lore.kernel.org/r/20240227125231.53127-1-hejunhao3@huawei.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/perf/hisilicon/hisi_uncore_uc_pmu.c | 42 ++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c index 636fb79647c8c..481dcc9e8fbf8 100644 --- a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c @@ -287,12 +287,52 @@ static u64 hisi_uc_pmu_read_counter(struct hisi_pmu *uc_pmu, return readq(uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); } -static void hisi_uc_pmu_write_counter(struct hisi_pmu *uc_pmu, +static bool hisi_uc_pmu_get_glb_en_state(struct hisi_pmu *uc_pmu) +{ + u32 val; + + val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); + return !!FIELD_GET(HISI_UC_EVENT_GLB_EN, val); +} + +static void hisi_uc_pmu_write_counter_normal(struct hisi_pmu *uc_pmu, struct hw_perf_event *hwc, u64 val) { writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); } +static void hisi_uc_pmu_write_counter_quirk_v2(struct hisi_pmu *uc_pmu, + struct hw_perf_event *hwc, u64 val) +{ + hisi_uc_pmu_start_counters(uc_pmu); + hisi_uc_pmu_write_counter_normal(uc_pmu, hwc, val); + hisi_uc_pmu_stop_counters(uc_pmu); +} + +static void hisi_uc_pmu_write_counter(struct hisi_pmu *uc_pmu, + struct hw_perf_event *hwc, u64 val) +{ + bool enable = hisi_uc_pmu_get_glb_en_state(uc_pmu); + bool erratum = uc_pmu->identifier == HISI_PMU_V2; + + /* + * HiSilicon UC PMU v2 suffers the erratum 162700402 that the + * PMU counter cannot be set due to the lack of clock under power + * saving mode. This will lead to error or inaccurate counts. + * The clock can be enabled by the PMU global enabling control. + * The irq handler and pmu_start() will call the function to set + * period. If the function under irq context, the PMU has been + * enabled therefore we set counter directly. Other situations + * the PMU is disabled, we need to enable it to turn on the + * counter clock to set period, and then restore PMU enable + * status, the counter can hold its value without a clock. + */ + if (enable || !erratum) + hisi_uc_pmu_write_counter_normal(uc_pmu, hwc, val); + else + hisi_uc_pmu_write_counter_quirk_v2(uc_pmu, hwc, val); +} + static void hisi_uc_pmu_enable_counter_int(struct hisi_pmu *uc_pmu, struct hw_perf_event *hwc) { -- 2.43.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel