From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19CDECD1284 for ; Thu, 4 Apr 2024 07:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SS1W+WIUNvfDLUjnocfcDW6A1Mad1/om95dQnGB65p8=; b=ZrfPb2zLsCci6h hM/IEKO9RxczKRxx23wfC9+yd4rcWTT3OgswOAVqylJvkeSN/Nr6c+UtqERzZtuBgW9/PEaR1T088 tnvLtSjhLxieBjgA7USSzy+N9enjPyTm6P7A7iskadp/MZjE//ozbVn1mNHEheZfDcxyLjHsCVfaS /1BNOVKOJP86s5CgfIALWgztiH2sEQmuKUd3WrybN0yHcjKhQIF1Okhcb5ivCxHOW3p+GbrkRRtqF ghdhtl2Bhg8uz8V8a3nuNTr+hKBWZ+N0JbKODyJQuWrN+gsvIE4EtDUePoG7uQcQESCC6LlpXavv5 xu2swRO5HznX7xLsN9Hg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rsHfL-00000001fBX-3Eet; Thu, 04 Apr 2024 07:37:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rsHfJ-00000001fAL-0wUw for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2024 07:37:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93A5D1595; Thu, 4 Apr 2024 00:38:10 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.56.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0B4BC3F64C; Thu, 4 Apr 2024 00:37:37 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com Cc: Anshuman Khandual Subject: [bootwrapper PATCH 2/2] aarch64: Disable trapping into EL3 while accessing FEAT_FGT2 registers Date: Thu, 4 Apr 2024 13:07:26 +0530 Message-Id: <20240404073726.947215-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240404073726.947215-1-anshuman.khandual@arm.com> References: <20240404073726.947215-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240404_003741_341476_56B6B057 X-CRM114-Status: UNSURE ( 7.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This disables trapping into EL3 while accessing Fine Grained Traps Enable 2 (i.e FEAT_FGT2) registers such as HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, HFGRTR2_EL2 and HFGWTR2_EL2 via setting SCR_EL3.FGTEN2. But first ensure that FEAT_FGT2 feature is implemented looking into ID_AA64MMFR0_EL1. Signed-off-by: Anshuman Khandual --- arch/aarch64/include/asm/cpu.h | 1 + arch/aarch64/init.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 124ef91..56f319a 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -57,6 +57,7 @@ #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_PIEN BIT(45) +#define SCR_EL3_FGTEN2 BIT(59) #define HCR_EL2_RES1 BIT(1) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 37cb45f..557266b 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -68,6 +68,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR0_EL1, FGT)) scr |= SCR_EL3_FGTEN; + if (mrs_field(ID_AA64MMFR0_EL1, FGT) >= 2) + scr |= SCR_EL3_FGTEN2; + if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) scr |= SCR_EL3_ECVEN; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel