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Fri, 05 Apr 2024 15:18:32 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 435FIVbG026932 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 Apr 2024 15:18:31 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 5 Apr 2024 08:18:30 -0700 Date: Fri, 5 Apr 2024 08:18:30 -0700 From: Elliot Berman To: Pavan Kondeti CC: Alex Elder , Srinivas Kandagatla , Murali Nalajal , Trilok Soni , Srivatsa Vaddagiri , Carl van Schaik , Philip Derrin , Prakruthi Deepak Heragu , Jonathan Corbet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio , Bjorn Andersson , Dmitry Baryshkov , "Fuad Tabba" , Sean Christopherson , "Andrew Morton" , , , , , , Subject: Re: [PATCH v17 11/35] virt: gunyah: Translate gh_rm_hyp_resource into gunyah_resource Message-ID: <20240405081735319-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240222-gunyah-v17-0-1e9da6763d38@quicinc.com> <20240222-gunyah-v17-11-1e9da6763d38@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CjpQNiJgepbUe_PWBObBh6vdhvVm1JNM X-Proofpoint-ORIG-GUID: CjpQNiJgepbUe_PWBObBh6vdhvVm1JNM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-05_16,2024-04-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 mlxlogscore=901 bulkscore=0 suspectscore=0 clxscore=1011 priorityscore=1501 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404050110 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240405_161851_235072_D4135DA7 X-CRM114-Status: GOOD ( 31.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 05, 2024 at 08:40:40AM +0530, Pavan Kondeti wrote: > On Thu, Feb 22, 2024 at 03:16:34PM -0800, Elliot Berman wrote: > > When booting a Gunyah virtual machine, the host VM may gain capabilities > > to interact with resources for the guest virtual machine. Examples of > > such resources are vCPUs or message queues. To use those resources, we > > need to translate the RM response into a gunyah_resource structure which > > are useful to Linux drivers. Presently, Linux drivers need only to know > > the type of resource, the capability ID, and an interrupt. > > > > On ARM64 systems, the interrupt reported by Gunyah is the GIC interrupt > > ID number and always a SPI or extended SPI. > > > > Signed-off-by: Elliot Berman > > --- > > arch/arm64/include/asm/gunyah.h | 36 ++++++++++++++++++++++ > > drivers/virt/gunyah/rsc_mgr.c | 67 +++++++++++++++++++++++++++++++++++++++++ > > drivers/virt/gunyah/rsc_mgr.h | 5 +++ > > include/linux/gunyah.h | 2 ++ > > 4 files changed, 110 insertions(+) > > > > diff --git a/arch/arm64/include/asm/gunyah.h b/arch/arm64/include/asm/gunyah.h > > new file mode 100644 > > index 0000000000000..0cd3debe22b64 > > --- /dev/null > > +++ b/arch/arm64/include/asm/gunyah.h > > @@ -0,0 +1,36 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. > > + */ > > +#ifndef _ASM_GUNYAH_H > > +#define _ASM_GUNYAH_H > > + > > +#include > > +#include > > + > > +static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq, > > + struct irq_fwspec *fwspec) > > +{ > > + /* Assume that Gunyah gave us an SPI or ESPI; defensively check it */ > > + if (WARN(virq < 32, "Unexpected virq: %d\n", virq)) { > > + return -EINVAL; > > + } else if (virq <= 1019) { > > + fwspec->param_count = 3; > > + fwspec->param[0] = 0; /* GIC_SPI */ > > + fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */ > > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; > > + } else if (WARN(virq < 4096, "Unexpected virq: %d\n", virq)) { > > + return -EINVAL; > > + } else if (virq < 5120) { > > + fwspec->param_count = 3; > > + fwspec->param[0] = 2; /* GIC_ESPI */ > > + fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */ > > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; > > + } else { > > + WARN(1, "Unexpected virq: %d\n", virq); > > + return -EINVAL; > > + } > > + return 0; > > +} > > + > > __get_intid_range() in gic-v3 driver looks more pleasing. Other than > that the logic for the translation looks good to me. Agreed, updated for v18. static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq, struct irq_fwspec *fwspec) { /* Assume that Gunyah gave us an SPI or ESPI; defensively check it */ switch (virq) { case 32 ... 1019: fwspec->param_count = 3; fwspec->param[0] = 0; /* GIC_SPI */ fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */ fwspec->param[2] = IRQ_TYPE_EDGE_RISING; break; case 4096 ... 5119: fwspec->param_count = 3; fwspec->param[0] = 2; /* GIC_ESPI */ fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */ fwspec->param[2] = IRQ_TYPE_EDGE_RISING; break; default: WARN(1, "Unexpected virq: %d\n", virq) return -EINVAL; } return 0; } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel