From: Will Deacon <will@kernel.org>
To: Yicong Yang <yangyicong@huawei.com>
Cc: mark.rutland@arm.com, catalin.marinas@arm.com,
broonie@kernel.org, james.morse@arm.com,
anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org,
jonathan.cameron@huawei.com,
shameerali.kolothum.thodi@huawei.com, prime.zeng@hisilicon.com,
fanghao11@huawei.com, yangyicong@hisilicon.com,
linuxarm@huawei.com, maz@kernel.org
Subject: Re: [PATCH v2 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime
Date: Thu, 11 Apr 2024 15:28:29 +0100 [thread overview]
Message-ID: <20240411142829.GA26681@willie-the-truck> (raw)
In-Reply-To: <20231130074609.58668-4-yangyicong@huawei.com>
On Thu, Nov 30, 2023 at 03:46:09PM +0800, Yicong Yang wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> On a VHE enabled host, the PMSCR_EL1 will be redirect to PMSCR_EL2
> and we're actually enabling E0SPE and E2SPE in the driver. This means
> the data from EL0&1 translation regime of a VM will not be profiled.
> So this patch tries to add the support of profiling EL0 and EL1 of
> a VM. Users can filter data of different exception level by using
> the perf's exclude_* attributes. The exclude_* decision is referred
> to Documentation/arch/arm64/perf.rst and the implementation of
> arm_pmuv3.
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> ---
> drivers/perf/arm_spe_pmu.c | 37 ++++++++++++++++++++++++++++++-------
> 1 file changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
> index 09570d4d63cd..a647d625f359 100644
> --- a/drivers/perf/arm_spe_pmu.c
> +++ b/drivers/perf/arm_spe_pmu.c
> @@ -316,21 +316,44 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event)
> static void arm_spe_pmu_set_pmscr(struct perf_event *event)
> {
> struct perf_event_attr *attr = &event->attr;
> - u64 reg = 0;
> + u64 pmscr_el1, pmscr_el12;
>
> - reg = arm_spe_event_to_pmscr(event);
> - if (!attr->exclude_user)
> - reg |= PMSCR_EL1x_E0SPE;
> + pmscr_el1 = pmscr_el12 = arm_spe_event_to_pmscr(event);
> +
> + /*
> + * Map the exclude_* descision to ELx according to
> + * Documentation/arch/arm64/perf.rst.
> + */
> + if (is_kernel_in_hyp_mode()) {
> + if (!attr->exclude_kernel && !attr->exclude_host)
> + pmscr_el1 |= PMSCR_EL1x_E1SPE;
>
> - if (!attr->exclude_kernel)
> - reg |= PMSCR_EL1x_E1SPE;
> + if (!attr->exclude_kernel && !attr->exclude_guest)
> + pmscr_el12 |= PMSCR_EL1x_E1SPE;
> +
> + if (!attr->exclude_user && !attr->exclude_host) {
> + pmscr_el1 |= PMSCR_EL1x_E0SPE;
> + pmscr_el12 |= PMSCR_EL1x_E0SPE;
> + }
Hmm, I don't understand this part. Doesn't this mean that setting
'exclude_host' to true will also exclude userspace (EL0) profiling for
the guest?
Will
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next prev parent reply other threads:[~2024-04-11 14:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-30 7:46 [PATCH v2 0/3] Enable the profiling of EL0&1 translation regime of ARM SPE Yicong Yang
2023-11-30 7:46 ` [PATCH v2 1/3] arm64/sysreg: Add PMSCR_EL12 and factor out the common fields Yicong Yang
2023-11-30 7:46 ` [PATCH v2 2/3] perf: arm_spe: Factor out PMSCR set/clear operations Yicong Yang
2023-11-30 7:46 ` [PATCH v2 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime Yicong Yang
2024-04-11 14:28 ` Will Deacon [this message]
2024-04-12 9:22 ` Yicong Yang
2024-04-12 9:59 ` Marc Zyngier
2024-04-12 10:12 ` Yicong Yang
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