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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvLmx-00000000twm-2cV7; Fri, 12 Apr 2024 18:38:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvLmu-00000000tuk-2smK; Fri, 12 Apr 2024 18:38:14 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 8EEEB6140D; Fri, 12 Apr 2024 18:38:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9E42C113CC; Fri, 12 Apr 2024 18:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712947091; bh=F6zQv5ic7tyHfVnV+5BzE9fGTieop/gUlPWBQ1/NTQM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TqNKaNJyrcbRforb/MYgMOxrEDl0SnFDz+UiLgKXR0VegcimDJL8+gNaAxjh9arLZ j62nWhmhH0h7D1Bmhba/CnW9u/YGgTofj+BAjD10gL0TDJCs0f3Z1UujiCzKi6GAFk YEK3dm5xQ8+PL2KeHe3w+isaK+CMqV7wVeCklahS/AVcxH4s+CpCV3GOFnMAoH1Gk8 IdV5QM/34y7EioeIdQiUM8Z/ntcFPAm3ef00weUono8+NlvVOID5lvimmTOKcm0lbr FeG93C8vNVD9g4HsuYhpsnenlo3aCiD7XrPo4S8dV5SLWn3U3VoSz1oBTBARD9gD+j IjG9UHOou+uXw== Date: Fri, 12 Apr 2024 19:38:04 +0100 From: Conor Dooley To: Evan Green Cc: Conor Dooley , Charlie Jenkins , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Message-ID: <20240412-employer-crier-c201704d22e3@spud> References: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com> <20240411-dev-charlie-support_thead_vector_6_9-v1-2-4af9815ec746@rivosinc.com> <20240412-tuesday-resident-d9d07e75463c@wendy> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240412_113812_888540_7404D236 X-CRM114-Status: GOOD ( 31.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0053185335834568953==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0053185335834568953== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="gRwXSR6OMoeFGriG" Content-Disposition: inline --gRwXSR6OMoeFGriG Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Apr 12, 2024 at 10:04:17AM -0700, Evan Green wrote: > On Fri, Apr 12, 2024 at 3:26=E2=80=AFAM Conor Dooley wrote: > > > > On Thu, Apr 11, 2024 at 09:11:08PM -0700, Charlie Jenkins wrote: > > > The riscv_cpuinfo struct that contains mvendorid and marchid is not > > > populated until all harts are booted which happens after the DT parsi= ng. > > > Use the vendorid/archid values from the DT if available or assume all > > > harts have the same values as the boot hart as a fallback. > > > > > > Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property= on older T-Head CPUs") > > > > If this is our only use case for getting the mvendorid/marchid stuff > > from dt, then I don't think we should add it. None of the devicetrees > > that the commit you're fixing here addresses will have these properties > > and if they did have them, they'd then also be new enough to hopefully > > not have "v" either - the issue is they're using whatever crap the > > vendor shipped. > > If we're gonna get the information from DT, we already have something > > that we can look at to perform the disable as the cpu compatibles give > > us enough information to make the decision. > > > > I also think that we could just cache the boot CPU's marchid/mvendorid, > > since we already have to look at it in riscv_fill_cpu_mfr_info(), avoid > > repeating these ecalls on all systems. > > > > Perhaps for now we could just look at the boot CPU alone? To my > > knowledge the systems that this targets all have homogeneous > > marchid/mvendorid values of 0x0. >=20 > It's possible I'm misinterpreting, but is the suggestion to apply the > marchid/mvendorid we find on the boot CPU and assume it's the same on > all other CPUs? Since we're reporting the marchid/mvendorid/mimpid to > usermode in a per-hart way, it would be better IMO if we really do > query marchid/mvendorid/mimpid on each hart. The problem with applying > the boot CPU's value everywhere is if we're ever wrong in the future > (ie that assumption doesn't hold on some machine), we'll only find out > about it after the fact. Since we reported the wrong information to > usermode via hwprobe, it'll be an ugly userspace ABI issue to clean > up. You're misinterpreting, we do get the values on all individually as they're brought online. This is only used by the code that throws a bone to people with crappy vendor dtbs that put "v" in riscv,isa when they support the unratified version. --gRwXSR6OMoeFGriG Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZhl/jAAKCRB4tDGHoIJi 0ptyAP0ZNjBpBCn7hL8p0/KqkB5iLRYcgUFzEfFnnLIR4Xu6bQEAnNsKHlMQNDHe Gwr2lxxHHiZdULO9EWHcunPE1hXT4w4= =sTMn -----END PGP SIGNATURE----- --gRwXSR6OMoeFGriG-- --===============0053185335834568953== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0053185335834568953==--