From: Liao Chang <liaochang1@huawei.com>
To: <catalin.marinas@arm.com>, <will@kernel.org>, <maz@kernel.org>,
<oliver.upton@linux.dev>, <james.morse@arm.com>,
<suzuki.poulose@arm.com>, <yuzenghui@huawei.com>,
<tglx@linutronix.de>, <mark.rutland@arm.com>, <ardb@kernel.org>,
<broonie@kernel.org>, <liaochang1@huawei.com>,
<anshuman.khandual@arm.com>, <miguel.luis@oracle.com>,
<joey.gouly@arm.com>, <ryan.roberts@arm.com>,
<jeremy.linton@arm.com>, <ericchancf@google.com>,
<kristina.martsenko@arm.com>, <robh@kernel.org>,
<scott@os.amperecomputing.com>, <songshuaishuai@tinylab.org>,
<shijie@os.amperecomputing.com>, <akpm@linux-foundation.org>,
<bhe@redhat.com>, <horms@kernel.org>, <mhiramat@kernel.org>,
<rmk+kernel@armlinux.org.uk>, <shahuang@redhat.com>,
<takakura@valinux.co.jp>, <dianders@chromium.org>,
<swboyd@chromium.org>, <sumit.garg@linaro.org>,
<frederic@kernel.org>, <reijiw@google.com>,
<akihiko.odaki@daynix.com>, <ruanjinjie@huawei.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <kvmarm@lists.linux.dev>
Subject: [PATCH v3 1/8] arm64/sysreg: Add definitions for immediate versions of MSR ALLINT
Date: Mon, 15 Apr 2024 06:47:51 +0000 [thread overview]
Message-ID: <20240415064758.3250209-2-liaochang1@huawei.com> (raw)
In-Reply-To: <20240415064758.3250209-1-liaochang1@huawei.com>
From: Mark Brown <broonie@kernel.org>
Encodings are provided for ALLINT which allow setting of ALLINT.ALLINT
using an immediate rather than requiring that a register be loaded with
the value to write. Since these don't currently fit within the scheme we
have for sysreg generation add manual encodings like we currently do for
other similar registers such as SVCR.
Since it is required that these immediate versions be encoded with xzr
as the source register provide asm wrapper which ensure this is the
case.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
---
arch/arm64/include/asm/nmi.h | 27 +++++++++++++++++++++++++++
arch/arm64/include/asm/sysreg.h | 2 ++
2 files changed, 29 insertions(+)
create mode 100644 arch/arm64/include/asm/nmi.h
diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h
new file mode 100644
index 000000000000..0c566c649485
--- /dev/null
+++ b/arch/arm64/include/asm/nmi.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022 ARM Ltd.
+ */
+#ifndef __ASM_NMI_H
+#define __ASM_NMI_H
+
+#ifndef __ASSEMBLER__
+
+#include <linux/cpumask.h>
+
+extern bool arm64_supports_nmi(void);
+
+#endif /* !__ASSEMBLER__ */
+
+static __always_inline void _allint_clear(void)
+{
+ asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr"));
+}
+
+static __always_inline void _allint_set(void)
+{
+ asm volatile(__msr_s(SYS_ALLINT_SET, "xzr"));
+}
+
+#endif
+
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e8999592f3a..b105773c57ca 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -167,6 +167,8 @@
* System registers, organised loosely by encoding but grouped together
* where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
*/
+#define SYS_ALLINT_CLR sys_reg(0, 1, 4, 0, 0)
+#define SYS_ALLINT_SET sys_reg(0, 1, 4, 1, 0)
#define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
#define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
--
2.34.1
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next prev parent reply other threads:[~2024-04-15 6:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 6:47 [PATCH v3 0/8] Rework the DAIF mask, unmask and track API Liao Chang
2024-04-15 6:47 ` Liao Chang [this message]
2024-05-03 16:00 ` [PATCH v3 1/8] arm64/sysreg: Add definitions for immediate versions of MSR ALLINT Mark Rutland
2024-05-06 12:12 ` Liao, Chang
2024-05-06 15:15 ` Mark Brown
2024-05-07 7:41 ` Liao, Chang
2024-05-07 14:52 ` Mark Brown
2024-06-03 3:26 ` Liao, Chang
2024-06-04 13:29 ` Mark Brown
2024-06-05 9:52 ` Liao, Chang
2024-06-14 4:00 ` Liao, Chang
2024-04-15 6:47 ` [PATCH v3 2/8] arm64/cpufeature: Detect PE support for FEAT_NMI Liao Chang
2024-04-15 6:47 ` [PATCH v3 3/8] arm64/nmi: Add Kconfig for NMI Liao Chang
2024-04-15 6:47 ` [PATCH v3 4/8] arm64: daifflags: Add logical exception masks covering DAIF + PMR + ALLINT Liao Chang
2024-04-15 6:47 ` [PATCH v3 5/8] arm64: Unify exception masking at entry and exit of exception Liao Chang
2024-04-15 6:47 ` [PATCH v3 6/8] arm64: Deprecate old local_daif_{mask,save,restore} Liao Chang
2024-04-15 6:47 ` [PATCH v3 7/8] irqchip/gic-v3: Improve the maintainability of NMI masking in GIC driver Liao Chang
2024-04-15 6:47 ` [PATCH v3 8/8] arm64: kprobe: Keep NMI maskabled while kprobe is stepping xol Liao Chang
2024-05-03 17:10 ` [PATCH v3 0/8] Rework the DAIF mask, unmask and track API Mark Rutland
2024-05-06 12:12 ` Liao, Chang
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