From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10076C4345F for ; Fri, 19 Apr 2024 13:30:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f8vNcUcbP3iOU9CV7IPwkYxUY42pVh+Vfjg5NaR4qko=; b=Mwee177u8INeA1 tmZ8QTICyN4MerTtvVfhjhBcwaZeLTzjKJVRTb+ecFEMungxmXUTjr+K4luPXuiOZP+kGVlNHrLvU hn27rn3uK+3H+dsF9d84GwEw7SUTPOtT6R9Q+8Tg/qj7EDBakUTD/1aU1nIEvFVPpO/lfZywnD2eU +wPDlfqn2OEz2UF7ol21JzDaVQLxxlaBkc0Y2HDwo1b6PDaXV1mCdLqF3cceWxpy3wVuD8pATk7rn LApfNeNqsJQFE6yQcX8p3Fw/EIQ82gTAAGGKx/klxWj4iSNG//V6rx7r5hwB3DWlHk9Lskk7JyEY0 kk2wKMT2X4dA/xCN0OpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxoK2-00000005lJH-0v7f; Fri, 19 Apr 2024 13:30:34 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxoJz-00000005lIZ-1LmR for linux-arm-kernel@lists.infradead.org; Fri, 19 Apr 2024 13:30:33 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id B4DF1CE1A95; Fri, 19 Apr 2024 13:30:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48960C072AA; Fri, 19 Apr 2024 13:30:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713533427; bh=GXF1iPLLsj+lPXqnRynd5BnS/PTOStGizUC5EOHysNs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=htnFnpLKUSBz/vJ9dnPp+b0bf9XprdmpWhRTyEsZvcP/PTxto6lTDWQfnMbtWPgFz HJ01QUIaGpU/39+h4NNSYULFKYqtWH6g8tWuYsLYdsPuVB6/e+EOYwGUVcIEgP2J0u mou9DWbhtW+FC/FMZ4RKaZR2x80a4bh12UfQQ0FHumxT3coPI1bZrYSLvG/dcBFnXq 2dEBxYm/V5myDO/Khh+DWJO6axW6VX15erkyG/qrJZWvb26wjwLmJ4JN/qYC2rFz+p hAWRMjm6R4hZvK8o+v8oLrpXGMpQJ79mllMN4bZQoY7DmLwyCh/oDnn97L0T1roXh7 Q7OmyNJKOl1lw== Date: Fri, 19 Apr 2024 14:30:20 +0100 From: Will Deacon To: Puranjay Mohan Cc: Catalin Marinas , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Zi Shen Lim , Xu Kuohai , Florent Revest , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: Re: [PATCH bpf-next] arm64, bpf: add internal-only MOV instruction to resolve per-CPU addrs Message-ID: <20240419133020.GC3148@willie-the-truck> References: <20240405091707.66675-1-puranjay12@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240405091707.66675-1-puranjay12@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240419_063031_748619_0DE60909 X-CRM114-Status: GOOD ( 27.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 05, 2024 at 09:17:07AM +0000, Puranjay Mohan wrote: > Support an instruction for resolving absolute addresses of per-CPU > data from their per-CPU offsets. This instruction is internal-only and > users are not allowed to use them directly. They will only be used for > internal inlining optimizations for now between BPF verifier and BPF > JITs. > = > Since commit 7158627686f0 ("arm64: percpu: implement optimised pcpu > access using tpidr_el1"), the per-cpu offset for the CPU is stored in > the tpidr_el1/2 register of that CPU. > = > To support this BPF instruction in the ARM64 JIT, the following ARM64 > instructions are emitted: > = > mov dst, src // Move src to dst, if src !=3D dst > mrs tmp, tpidr_el1/2 // Move per-cpu offset of the current cpu in tmp. > add dst, dst, tmp // Add the per cpu offset to the dst. > = > If CONFIG_SMP is not defined, then nothing is emitted if src =3D=3D dst, = and > mov dst, src is emitted if dst !=3D src. > = > To measure the performance improvement provided by this change, the > benchmark in [1] was used: > = > Before: > glob-arr-inc : 23.597 =B1 0.012M/s > arr-inc : 23.173 =B1 0.019M/s > hash-inc : 12.186 =B1 0.028M/s > = > After: > glob-arr-inc : 23.819 =B1 0.034M/s > arr-inc : 23.285 =B1 0.017M/s > hash-inc : 12.419 =B1 0.011M/s > = > [1] https://github.com/anakryiko/linux/commit/8dec900975ef > = > Signed-off-by: Puranjay Mohan > --- > arch/arm64/include/asm/insn.h | 7 +++++++ > arch/arm64/lib/insn.c | 11 +++++++++++ > arch/arm64/net/bpf_jit.h | 6 ++++++ > arch/arm64/net/bpf_jit_comp.c | 16 ++++++++++++++++ > 4 files changed, 40 insertions(+) > = > diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h > index db1aeacd4cd9..d16d68550c22 100644 > --- a/arch/arm64/include/asm/insn.h > +++ b/arch/arm64/include/asm/insn.h > @@ -135,6 +135,11 @@ enum aarch64_insn_special_register { > AARCH64_INSN_SPCLREG_SP_EL2 =3D 0xF210 > }; > = > +enum aarch64_insn_system_register { > + AARCH64_INSN_SYSREG_TPIDR_EL1 =3D 0xC684, > + AARCH64_INSN_SYSREG_TPIDR_EL2 =3D 0xE682, > +}; I think these constants should have bit 15 as 0... > + > enum aarch64_insn_variant { > AARCH64_INSN_VARIANT_32BIT, > AARCH64_INSN_VARIANT_64BIT > @@ -686,6 +691,8 @@ u32 aarch64_insn_gen_cas(enum aarch64_insn_register r= esult, > } > #endif > u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type); > +u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result, > + enum aarch64_insn_system_register sysreg); > = > s32 aarch64_get_branch_offset(u32 insn); > u32 aarch64_set_branch_offset(u32 insn, s32 offset); > diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c > index a635ab83fee3..b008a9b46a7f 100644 > --- a/arch/arm64/lib/insn.c > +++ b/arch/arm64/lib/insn.c > @@ -1515,3 +1515,14 @@ u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type= type) > = > return insn; > } > + > +u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result, > + enum aarch64_insn_system_register sysreg) > +{ > + u32 insn =3D aarch64_insn_get_mrs_value(); > + > + insn &=3D ~GENMASK(19, 0); > + insn |=3D sysreg << 5; ... otherwise you're shifting into the opcode bits at the top. It works out because bit 20 is 1, but I think it would be better to rework your aarch64_insn_system_register values. > + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, > + insn, result); > +} > diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h > index 23b1b34db088..b627ef7188c7 100644 > --- a/arch/arm64/net/bpf_jit.h > +++ b/arch/arm64/net/bpf_jit.h > @@ -297,4 +297,10 @@ > #define A64_ADR(Rd, offset) \ > aarch64_insn_gen_adr(0, offset, Rd, AARCH64_INSN_ADR_TYPE_ADR) > = > +/* MRS */ > +#define A64_MRS_TPIDR_EL1(Rt) \ > + aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL1) > +#define A64_MRS_TPIDR_EL2(Rt) \ > + aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL2) > + > #endif /* _BPF_JIT_H */ > diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c > index 76b91f36c729..e9ad9f257a18 100644 > --- a/arch/arm64/net/bpf_jit_comp.c > +++ b/arch/arm64/net/bpf_jit_comp.c > @@ -877,6 +877,17 @@ static int build_insn(const struct bpf_insn *insn, s= truct jit_ctx *ctx, > emit(A64_ORR(1, tmp, dst, tmp), ctx); > emit(A64_MOV(1, dst, tmp), ctx); > break; > + } else if (insn_is_mov_percpu_addr(insn)) { > + if (dst !=3D src) > + emit(A64_MOV(1, dst, src), ctx); > +#ifdef CONFIG_SMP CONFIG_SMP is always 'y' on arm64. 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