From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29AB4C4345F for ; Fri, 19 Apr 2024 23:31:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IDX4FWgRxS4krbubdeoC9pWTM4i7vkCa8s6z75mlypU=; b=xwl3O9GjsjeCcR nNOAm7EQUzW9LOvMhHpzpxn/sW1WNxUOH1YJOthTZ+oOpP+b20JFgzGEX1nx36BklTFUf/KnXDLWD /OVuBfukJud4QCe6wjc1EVGCb8RQ24as4YlGPQfLs7qqhehbniwvySqbb+p0RW/okeVDh/x10ih+T 3dNptGh81S0/PNgVKPCQX4of/yJBVCwOCO22GNz1fcy2vd4l9RqHxKeUAjiddHHaDZYImwUUKiskj FZIYkuSqoCD97HwCL+oyL94bMR4wNXi4gzhWcjqlVI+ORZxkTYbjldn2Cm5z6q0rpg9fgGBW6QuFG DF+qoWkinRvdJCM0x+Dw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxxhd-00000007GhQ-1Sbn; Fri, 19 Apr 2024 23:31:33 +0000 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxxhZ-00000007GgQ-1Sq9 for linux-arm-kernel@lists.infradead.org; Fri, 19 Apr 2024 23:31:30 +0000 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43JMsPNc025597; Fri, 19 Apr 2024 23:31:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= date:from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=qcppdkim1; bh=7YnOs/zIN96oMB3AwWlXg 64tPuvFDKMPlHsSp9oJv1I=; b=p6dZWNO1tSiHG2IBHs697YnUU6PtAm4t1qJml /CsthJIMrWP0pL/iukK6CKVPqKADiZ5a7v8m+mUFCw7IQM4Tc2AQtILnQQjY9L0N xabs1UGVHrWYVtNOKeMairbBSR4ogrT2LbiRZ6t3Qnnant9r2Eh1iyFsURos8wm6 tS62m00iiCjsVOqO1oIIVTedot3sbo9u16EFIivfkNh+WF6RpNFgaUNxRySXXOh8 LSABk1GO4Ajley8x/kuIAzvChn5wQf2lrez7KPAG7T9IINAyTgHluFdJ7yQWzCeJ B686XdG5N7wun21PfCGLIOODR9/9yeJm5PHcp7UMv0GTqLYtw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xkkss9uc7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Apr 2024 23:31:19 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43JNVIsT003709 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Apr 2024 23:31:18 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 19 Apr 2024 16:31:17 -0700 Date: Fri, 19 Apr 2024 16:31:17 -0700 From: Elliot Berman To: Sudeep Holla CC: Bjorn Andersson , Konrad Dybcio , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , , Subject: Re: [PATCH v2 0/4] Implement vendor resets for PSCI SYSTEM_RESET2 Message-ID: <20240419134542691-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> <20240417140957985-0700.eberman@hu-eberman-lv.qualcomm.com> <20240419085345.4ovebbbmcabo3f73@bogus> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240419085345.4ovebbbmcabo3f73@bogus> X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ptwZxpIb3YjMjehV0iVZZt6crq1l_sl3 X-Proofpoint-GUID: ptwZxpIb3YjMjehV0iVZZt6crq1l_sl3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-19_15,2024-04-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=949 adultscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404190183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240419_163129_565326_C82D0E64 X-CRM114-Status: GOOD ( 38.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 19, 2024 at 09:53:45AM +0100, Sudeep Holla wrote: > On Wed, Apr 17, 2024 at 02:54:41PM -0700, Elliot Berman wrote: > > On Tue, Apr 16, 2024 at 10:35:22AM +0100, Sudeep Holla wrote: > > > On Sun, Apr 14, 2024 at 12:30:23PM -0700, Elliot Berman wrote: > > > > The PSCI SYSTEM_RESET2 call allows vendor firmware to define additional > > > > reset types which could be mapped to the reboot argument. > > > > > > > > Setting up reboot on Qualcomm devices can be inconsistent from chipset > > > > to chipset. > > > > > > That doesn't sound good. Do you mean PSCI SYSTEM_RESET doesn't work as > > > expected ? Does it mean it is not conformant to the specification ? > > > > > > > I was motivating the reason for using SYSTEM_RESET2. How to set the PMIC > > register and IMEM cookie can change between chipsets. Using > > SYSTEM_RESET2 alows us to abstract how to perform the reset. > > Fair enough. But I assume you are not providing the details of PMIC register > or IMEM cookie via DT. Kernel doesn't need this info. > > Anyways you did confirm if PSCI SYSTEM_RESET works as expected or not. That > is default and must work. > Yes, SYSTEM_RESET works on Quacomm firmware. The bindings disallow trying to override the default reboot. (reboot command = NULL or "") The PSCI parsing of the DT also doesn't have any of the special handling to deal with "mode-normal". > > > > Generally, there is a PMIC register that gets written to > > > > decide the reboot type. There is also sometimes a cookie that can be > > > > written to indicate that the bootloader should behave differently than a > > > > regular boot. These knobs evolve over product generations and require > > > > more drivers. Qualcomm firmwares are beginning to expose vendor > > > > SYSTEM_RESET2 types to simplify driver requirements from Linux. > > > > > > > > > > Why can't this be fully userspace driven ? What is the need to keep the > > > cookie in the DT ? > > > > As Dmitry pointed out, this information isn't discoverable. I suppose > > we could technically use bootconfig or kernel command-line to convey the > > map although I think devicetree is the right spot for this mapping. > > > > Yes and as usual DT has become dumping ground for firmware that don't > make things discoverable. Make crap that Qcom puts in the DT are firmware > related and can be make discoverable. Anyways it is sad that no efforts > to make it so are done as DT is always there to provide shortcuts. > > > - Other vendor-specific bits for PSCI are described in the devicetree. > > One example is the suspend param (e.g. the StateID) for cpu idle > > states. > > You are right, but that is the only example I can see and it was done > in very early days of PSCI. It shouldn't be example if there are better > ways. > > > - Describing firmware bits in the DT isn't unprecedented, and putting > > this information outside the DT means that other OSes (besides Linux) > > need their own way to convey this information. > > Correct but it can be Qcom specific firmware interface. There are so many > already. This splitting information between firmware and DT works well > for vertically integrated things which probably is the case with most of > Qcom SoCs but it is prone to issues if DT and firmware mismatch. Firmware > discovery eliminates such issues. > I worry about designing interfaces both in Qualcomm firmware and in the PSCI driver which doesn't really suit handling the discovery. We can implement the dynamic discovery mechanims once there is a board which needs it. Thanks, Elliot _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel