From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7665C4345F for ; Thu, 25 Apr 2024 14:31:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=DLfN8ds7NaTnau/BVd9kWYdtFqE18h8403wVBkUofS0=; b=PATK6EtCD8Xkpj a5oS/4Z7ULOxfIFA+kkOO7K/YDvfBG1HTc2xbplYpZvVEPU5BSPTRhRyCPKTZYCQ58K7gvfzrl1nQ Uq6ug5io1EWp1B10yW7LmVY6YDY/EzWsZMKF/ExRACeCU+HQAiKuTU+fYlP200i5jF/1W+FZKPQvs IQJH0rZpIaBsfNvXik8g8NUBKFUzHGeUfdzHtk0Y2mKPSYWKs2gt6mIKrVK4weYPkOSluXdJn849O xW3lA8vvKcDfl8lPKLmNwPd9o+cO+ndqh1w1Q+sHT7cuEy1XVyyaqCnddMt7+YrTj2mwHKVOZE5d+ VSR2elWC2DR7dGzD49Pg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s007c-00000008ppy-24zK; Thu, 25 Apr 2024 14:30:48 +0000 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s007Z-00000008poe-2Vj6 for linux-arm-kernel@lists.infradead.org; Thu, 25 Apr 2024 14:30:47 +0000 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43P8dnHb012478; Thu, 25 Apr 2024 07:30:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=pfpt0220; bh=YypH+pGp IYpH7WBXp4Imc9+sq/Tm4UKy97IIMOK/RmE=; b=jXlj5TzP4xYtxzN9A1aIJOHP sTEiZk96fD1s7nMhlVFPgeiqN6P7DJ2u//RwjecMNEGrkAfe0MkZJSZZXFV0RkT6 4nFDvhPP0s1PO0f7o/WODgqY9zrwmwErkncYiHfiGVnyYYgApCuYazRqIpnzytTP xSR7KiAg1nDklymgz//8Rb1QSCrnUd19VF8WLKBk4q/ApFys8Lcfkko/ye5RpEqG C1Yj9Jk1DtxUxjP0fTQoOny4hfJJd86Ow7ceaVwz3z1j6QLCeNc+AI1Pl1JL0af+ xPiXXnftY/5lKZ05ozy+qoSBv/XbNGSXi/i8ZiyPTn0tPRMei760UYtLd6WGjg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xpxn1gfgw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Apr 2024 07:30:23 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 25 Apr 2024 07:30:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 25 Apr 2024 07:30:22 -0700 Received: from cn10ka.sclab.marvell.com (unknown [10.106.49.40]) by maili.marvell.com (Postfix) with ESMTP id BDE213F704A; Thu, 25 Apr 2024 07:30:21 -0700 (PDT) From: Tanmay Jagdale To: , , , , , , , , CC: , , , , , , Tanmay Jagdale Subject: [PATCH V3 0/2] iommu/arm-smmu-v3: Add support for ECMDQ register mode Date: Thu, 25 Apr 2024 07:30:13 -0700 Message-ID: <20240425143013.52292-1-tanmay@marvell.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Proofpoint-GUID: 1A7ExhV2ir6IOX6E4BdKfJKKUekojyoO X-Proofpoint-ORIG-GUID: 1A7ExhV2ir6IOX6E4BdKfJKKUekojyoO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-25_14,2024-04-25_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240425_073045_797870_B98EE4B1 X-CRM114-Status: GOOD ( 13.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Resending the patches by Zhen Lei that add support for SMMU ECMDQ feature. Tested this feature on a Marvell SoC by implementing a smmu-test driver. This test driver spawns a thread per CPU and each thread keeps sending map, table-walk and unmap requests for a fixed duration. Using this test driver, we compared ECMDQ vs SMMU with software batching support and saw ~5% improvement with ECMDQ. Performance numbers are mentioned below: Total Requests Average Requests Difference Per CPU wrt ECMDQ ----------------------------------------------------------------- ECMDQ 239286381 2991079 CMDQ Batch Size 1 228232187 2852902 -4.62% CMDQ Batch Size 32 233465784 2918322 -2.43% CMDQ Batch Size 64 231679588 2895994 -3.18% CMDQ Batch Size 128 233189030 2914862 -2.55% CMDQ Batch Size 256 230965773 2887072 -3.48% v2 --> v3: 1. Rebased on linux 6.9-rc5 v1 --> v2: 1. Drop patch "iommu/arm-smmu-v3: Add arm_smmu_ecmdq_issue_cmdlist() for non-shared ECMDQ" in v1 2. Drop patch "iommu/arm-smmu-v3: Add support for less than one ECMDQ per core" in v1 3. Replace rwlock with IPI to support lockless protection against the write operation to bit 'ERRACK' during error handling and the read operation to bit 'ERRACK' during command insertion. 4. Standardize variable names. - struct arm_smmu_ecmdq *__percpu *ecmdq; + struct arm_smmu_ecmdq *__percpu *ecmdqs; 5. Add member 'iobase' to struct arm_smmu_device to record the start physical address of the SMMU, to replace translation operation (vmalloc_to_pfn(smmu->base) << PAGE_SHIFT) + phys_addr_t iobase; - smmu_dma_base = (vmalloc_to_pfn(smmu->base) << PAGE_SHIFT); 6. Cancel below union. Whether ECMDQ is enabled is determined only based on 'ecmdq_enabled'. - union { - u32 nr_ecmdq; - u32 ecmdq_enabled; - }; + u32 nr_ecmdq; + bool ecmdq_enabled; 7. Eliminate some sparse check warnings. For example. - struct arm_smmu_ecmdq *ecmdq; + struct arm_smmu_ecmdq __percpu *ecmdq; Zhen Lei (2): iommu/arm-smmu-v3: Add support for ECMDQ register mode iommu/arm-smmu-v3: Ensure that a set of associated commands are inserted in the same ECMDQ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 261 +++++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 33 +++ 2 files changed, 286 insertions(+), 8 deletions(-) -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel