From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A340C19F53 for ; Tue, 30 Apr 2024 10:46:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2jjdqyBg7qrkLfWAhUdvXGBqZgzc+llcY6o4HmFpkgc=; b=ZYLe9XFiFWMW5i vC28PEavsctrjigZ00iUhLyEKMnAO4T1FLv2uVPc1+eSP3II7+7B8naqCtPh/4+i+N+RXH6DFdlWJ YyPlV6F7retnaNLAGasBpOYcB9j/L1yfnSb8YEukPIkFL7EQBKU6rrfce9TCQ+gYvE664iTcxwkNa NfeicR3o8Tg+1MvCvmvI+oM3P2c0/anWgSB4X6OkIiPHn1vhayzh0xUFc9e3I17B1zJKczzpvlr91 4fEHaYf0dshQiATcTL6ylocXkR5itnya4LaMUcjoR+dJJQdyI+zRvCQbT6KGtyyHSjkP8Huru6uvg HxpyehwwyWKQudDWiVuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1l0P-000000063br-0hTi; Tue, 30 Apr 2024 10:46:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1l0M-000000063al-2rLz for linux-arm-kernel@lists.infradead.org; Tue, 30 Apr 2024 10:46:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 152CD2F4; Tue, 30 Apr 2024 03:46:58 -0700 (PDT) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1FF353F73F; Tue, 30 Apr 2024 03:46:30 -0700 (PDT) Date: Tue, 30 Apr 2024 11:46:27 +0100 From: Andre Przywara To: Dragan Simic Cc: linux-sunxi@lists.linux.dev, wens@csie.org, jernej.skrabec@gmail.com, samuel@sholland.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Message-ID: <20240430114627.0cfcd14a@donnerap.manchester.arm.com> In-Reply-To: <6fdeb49d57ccccca62e4f43dbe9475e3@manjaro.org> References: <6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org> <49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org> <20240430001002.4797e4e3@minigeek.lan> <6fdeb49d57ccccca62e4f43dbe9475e3@manjaro.org> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240430_034634_807492_3669D110 X-CRM114-Status: GOOD ( 26.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 30 Apr 2024 02:01:42 +0200 Dragan Simic wrote: Hi Dragan, > Hello Andre, > > On 2024-04-30 01:10, Andre Przywara wrote: > > On Sun, 28 Apr 2024 13:40:36 +0200 > > Dragan Simic wrote: > > > >> Add missing cache information to the Allwinner H6 SoC dtsi, to allow > >> the userspace, which includes lscpu(1) that uses the virtual files > >> provided > >> by the kernel under the /sys/devices/system/cpu directory, to display > >> the > >> proper H6 cache information. > >> > >> Adding the cache information to the H6 SoC dtsi also makes the > >> following > >> warning message in the kernel log go away: > >> > >> cacheinfo: Unable to detect cache hierarchy for CPU 0 > >> > >> The cache parameters for the H6 dtsi were obtained and partially > >> derived > >> by hand from the cache size and layout specifications found in the > >> following > >> datasheets and technical reference manuals: > >> > >> - Allwinner H6 V200 datasheet, version 1.1 > >> - ARM Cortex-A53 revision r0p3 TRM, version E > >> > >> For future reference, here's a brief summary of the documentation: > >> > >> - All caches employ the 64-byte cache line length > >> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative > >> instruction > >> cache and 32 KB of L1 4-way, set-associative data cache > >> - The entire SoC has 512 KB of unified L2 16-way, set-associative > >> cache > >> > >> Signed-off-by: Dragan Simic > > > > I can confirm that the data below matches the manuals, but also the > > decoding of the architectural cache type registers (CCSIDR_EL1): > > L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line > > L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line > > L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line > > Thank you very much for reviewing my patch in such a detailed way! > It's good to know that the values in the Allwinner datasheets match > with the observed reality, so to speak. :) YW, and yes, I like to double check things when it comes to Allwinner documentation ;-) And it was comparably easy for this problem. Out of curiosity: what triggered that patch? Trying to get rid of false warning/error messages? And do you plan to address the H616 as well? It's a bit more tricky there, since there are two die revisions out: one with 256(?)KB of L2, one with 1MB(!). We know how to tell them apart, so I could provide some TF-A code to patch that up in the DT. The kernel DT copy could go with 256KB then. Cheers, Andre. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel