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Thu, 02 May 2024 02:21:17 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4422LHSh029273 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 2 May 2024 02:21:17 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 1 May 2024 19:21:16 -0700 Date: Wed, 1 May 2024 19:21:16 -0700 From: Elliot Berman To: Sudeep Holla CC: Florian Fainelli , Bjorn Andersson , Konrad Dybcio , "Sebastian Reichel" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , "Lorenzo Pieralisi" , Mark Rutland , Bartosz Golaszewski , "Satya Durga Srinivasu Prabhala" , Melody Olvera , Shivendra Pratap , , , , Subject: Re: [PATCH v2 0/4] Implement vendor resets for PSCI SYSTEM_RESET2 Message-ID: <20240501190823313-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240414-arm-psci-system_reset2-vendor-reboots-v2-0-da9a055a648f@quicinc.com> <48f366f5-4a17-474c-a8e3-6d79c9092d62@broadcom.com> <20240419123847.ica22nft3sejqnm7@bogus> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240419123847.ica22nft3sejqnm7@bogus> X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: V901gX_zoIsSIZykcHNca33lKpbonAM7 X-Proofpoint-ORIG-GUID: V901gX_zoIsSIZykcHNca33lKpbonAM7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-01_16,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405020008 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240501_192128_677115_58F8F61C X-CRM114-Status: GOOD ( 33.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 19, 2024 at 01:38:47PM +0100, Sudeep Holla wrote: > On Wed, Apr 17, 2024 at 10:50:07AM -0700, Florian Fainelli wrote: > > On 4/16/24 02:35, Sudeep Holla wrote: > > > On Sun, Apr 14, 2024 at 12:30:23PM -0700, Elliot Berman wrote: > > > > The PSCI SYSTEM_RESET2 call allows vendor firmware to define additional > > > > reset types which could be mapped to the reboot argument. > > > > > > > > Setting up reboot on Qualcomm devices can be inconsistent from chipset > > > > to chipset. > > > > > > That doesn't sound good. Do you mean PSCI SYSTEM_RESET doesn't work as > > > expected ? Does it mean it is not conformant to the specification ? > > > > > > > Generally, there is a PMIC register that gets written to > > > > decide the reboot type. There is also sometimes a cookie that can be > > > > written to indicate that the bootloader should behave differently than a > > > > regular boot. These knobs evolve over product generations and require > > > > more drivers. Qualcomm firmwares are beginning to expose vendor > > > > SYSTEM_RESET2 types to simplify driver requirements from Linux. > > > > > > > > > > Why can't this be fully userspace driven ? What is the need to keep the > > > cookie in the DT ? > > > > > > > > > > Using the second example in the Device Tree: > > > > mode-bootloader = <1 2>; > > > > are you suggesting that within psci_vendor_sys_reset2() we would look at the > > data argument and assume that we have something like this in memory: > > > > const char *cmd = data; > > > > cmd[] = "bootloader 2" > > > > where "bootloader" is the reboot command, and "2" is the cookie? From an > > util-linux, busybox, toybox, etc. we would have to concatenate those > > arguments with a space, but I suppose that would be doable. > > > > Yes that was my thought when I wrote the email. But since I have looked at > existing bindings and support in the kernel in little more detail I would say. > So I am not sure what would be the better choice for PSCI SYSTEM_RESET2 > especially when there is some ground support to build. > > So I am open for alternatives including this approach. If we can't go with the DT approach, my preference would be to go with a bootconfig and sysfs for controlling the mappings, although I don't think userspace need/should control the mappings of cmd -> cookies. I wanted to check if you are okay with proceeding with the reboot-mode DT bindings approach unless we have some other better standard? If yes, do you have any preference based on Konrad's comment [1]? I can send out v3 with the couple comments from Dmitry and Krzysztof's addressed. Thanks, Elliot [1]: https://lore.kernel.org/all/20240419123847.ica22nft3sejqnm7@bogus/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel