From: Francesco Dolcini <francesco@dolcini.it>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, danishanwar@ti.com,
srk@ti.com
Subject: Re: [PATCH v2 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
Date: Tue, 21 May 2024 22:09:09 +0200 [thread overview]
Message-ID: <20240521200909.GA3707@francesco-nb> (raw)
In-Reply-To: <20240520101149.3243151-2-s-vadapalli@ti.com>
On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote:
> TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
> PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
> these PCIe instances.
What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to
add all 3, not just the first twos.
Francesco
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next prev parent reply other threads:[~2024-05-21 20:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 10:11 [PATCH v2 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
2024-05-21 20:09 ` Francesco Dolcini [this message]
2024-05-22 10:21 ` Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
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