[PATCH 1/2] dt-bindings: iio: adc: amlogic,meson-saradc: add GXLX SoC compatible

[PATCH 1/2] dt-bindings: iio: adc: amlogic,meson-saradc: add GXLX SoC compatible

[Christian Hewitt]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Add support for the GXLX SoC. GXLX is very similar to GXL but has three
additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 .../devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
index 7e8328e9ce13..b2fef72267b4 100644
--- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -23,6 +23,7 @@ properties:
               - amlogic,meson8m2-saradc
               - amlogic,meson-gxbb-saradc
               - amlogic,meson-gxl-saradc
+              - amlogic,meson-gxlx-saradc
               - amlogic,meson-gxm-saradc
               - amlogic,meson-axg-saradc
               - amlogic,meson-g12a-saradc
-- 
2.34.1


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[PATCH 2/2] iio: adc: meson: add support for the GXLX SoC

[Christian Hewitt]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

The SARADC IP on GXLX is identical to the one found on GXL SoCs: except
GXLX requires poking the first three bits in the MESON_SAR_ADC_REG12
register to get the three MPLL clocks (used as clock generators for the
audio frequencies) to work. Register bits are from the vendor kernel.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/iio/adc/meson_saradc.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 13b473d8c6c7..200eb8271617 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -160,6 +160,11 @@
 	#define MESON_SAR_ADC_REG11_EOC                         BIT(1)
 	#define MESON_SAR_ADC_REG11_VREF_SEL                    BIT(0)
 
+#define MESON_SAR_ADC_REG12					0x30
+	#define MESON_SAR_ADC_REG12_MPLL0_UNKNOWN		BIT(0)
+	#define MESON_SAR_ADC_REG12_MPLL1_UNKNOWN		BIT(1)
+	#define MESON_SAR_ADC_REG12_MPLL2_UNKNOWN		BIT(2)
+
 #define MESON_SAR_ADC_REG13					0x34
 	#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK	GENMASK(13, 8)
 
@@ -327,6 +332,7 @@ struct meson_sar_adc_param {
 	u8					vref_select;
 	u8					cmv_select;
 	u8					adc_eoc;
+	bool					mpll_clock_bits;
 	enum meson_sar_adc_vref_sel		vref_volatge;
 };
 
@@ -1009,6 +1015,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
 				    priv->param->cmv_select);
 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
 				   MESON_SAR_ADC_REG11_CMV_SEL, regval);
+
+		if (priv->param->mpll_clock_bits)
+			regmap_write(priv->regmap, MESON_SAR_ADC_REG12,
+				     MESON_SAR_ADC_REG12_MPLL0_UNKNOWN |
+				     MESON_SAR_ADC_REG12_MPLL1_UNKNOWN |
+				     MESON_SAR_ADC_REG12_MPLL2_UNKNOWN);
 	}
 
 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
@@ -1241,6 +1253,17 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
 	.cmv_select = 1,
 };
 
+static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = {
+	.has_bl30_integration = true,
+	.clock_rate = 1200000,
+	.regmap_config = &meson_sar_adc_regmap_config_gxbb,
+	.resolution = 12,
+	.disable_ring_counter = 1,
+	.vref_voltage = VREF_VOLTAGE_1V8,
+	.cmv_select = true,
+	.mpll_clock_bits = true,
+};
+
 static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
 	.has_bl30_integration = true,
 	.clock_rate = 1200000,
@@ -1293,6 +1316,11 @@ static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
 	.name = "meson-gxl-saradc",
 };
 
+static const struct meson_sar_adc_data meson_sar_adc_gxlx_data = {
+	.param = &meson_sar_adc_gxlx_param,
+	.name = "meson-gxlx-saradc",
+};
+
 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
 	.param = &meson_sar_adc_gxl_param,
 	.name = "meson-gxm-saradc",
@@ -1324,6 +1352,9 @@ static const struct of_device_id meson_sar_adc_of_match[] = {
 	}, {
 		.compatible = "amlogic,meson-gxl-saradc",
 		.data = &meson_sar_adc_gxl_data,
+	}, {
+		.compatible = "amlogic,meson-gxlx-saradc",
+		.data = &meson_sar_adc_gxlx_data,
 	}, {
 		.compatible = "amlogic,meson-gxm-saradc",
 		.data = &meson_sar_adc_gxm_data,
-- 
2.34.1


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Re: [PATCH 1/2] dt-bindings: iio: adc: amlogic,meson-saradc: add GXLX SoC compatible

[Krzysztof Kozlowski]

On 04/06/2024 07:54, Christian Hewitt wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> Add support for the GXLX SoC. GXLX is very similar to GXL but has three
> additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC

[kernel test robot]

Hi Christian,

kernel test robot noticed the following build errors:

[auto build test ERROR on jic23-iio/togreg]
[also build test ERROR on robh/for-next linus/master v6.10-rc2 next-20240604]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Hewitt/iio-adc-meson-add-support-for-the-GXLX-SoC/20240604-135606
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link:    https://lore.kernel.org/r/20240604055431.3313961-2-christianshewitt%40gmail.com
patch subject: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC
config: arm-defconfig (https://download.01.org/0day-ci/archive/20240604/202406041751.elQWr6cj-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240604/202406041751.elQWr6cj-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406041751.elQWr6cj-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/iio/adc/meson_saradc.c:1262:18: error: use of undeclared identifier 'VREF_VOLTAGE_1V8'
           .vref_voltage = VREF_VOLTAGE_1V8,
                           ^
   1 error generated.


vim +/VREF_VOLTAGE_1V8 +1262 drivers/iio/adc/meson_saradc.c

  1255	
  1256	static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = {
  1257		.has_bl30_integration = true,
  1258		.clock_rate = 1200000,
  1259		.regmap_config = &meson_sar_adc_regmap_config_gxbb,
  1260		.resolution = 12,
  1261		.disable_ring_counter = 1,
> 1262		.vref_voltage = VREF_VOLTAGE_1V8,
  1263		.cmv_select = true,
  1264		.mpll_clock_bits = true,
  1265	};
  1266	

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Re: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC

[kernel test robot]

Hi Christian,

kernel test robot noticed the following build errors:

[auto build test ERROR on jic23-iio/togreg]
[also build test ERROR on robh/for-next linus/master v6.10-rc2 next-20240604]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Hewitt/iio-adc-meson-add-support-for-the-GXLX-SoC/20240604-135606
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link:    https://lore.kernel.org/r/20240604055431.3313961-2-christianshewitt%40gmail.com
patch subject: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20240604/202406041738.6Dy1cRih-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240604/202406041738.6Dy1cRih-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406041738.6Dy1cRih-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/iio/adc/meson_saradc.c:1262:10: error: 'const struct meson_sar_adc_param' has no member named 'vref_voltage'; did you mean 'vref_volatge'?
    1262 |         .vref_voltage = VREF_VOLTAGE_1V8,
         |          ^~~~~~~~~~~~
         |          vref_volatge
>> drivers/iio/adc/meson_saradc.c:1262:25: error: 'VREF_VOLTAGE_1V8' undeclared here (not in a function)
    1262 |         .vref_voltage = VREF_VOLTAGE_1V8,
         |                         ^~~~~~~~~~~~~~~~


vim +1262 drivers/iio/adc/meson_saradc.c

  1255	
  1256	static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = {
  1257		.has_bl30_integration = true,
  1258		.clock_rate = 1200000,
  1259		.regmap_config = &meson_sar_adc_regmap_config_gxbb,
  1260		.resolution = 12,
  1261		.disable_ring_counter = 1,
> 1262		.vref_voltage = VREF_VOLTAGE_1V8,
  1263		.cmv_select = true,
  1264		.mpll_clock_bits = true,
  1265	};
  1266	

-- 
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https://github.com/intel/lkp-tests/wiki

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Re: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC

[Christian Hewitt]

> On 4 Jun 2024, at 1:10 PM, kernel test robot <lkp@intel.com> wrote:
> 
> kernel test robot noticed the following build errors:

Apologies. Build errors are because I wrongly imagined this dependent series from Martin to be merged:

https://patchwork.kernel.org/project/linux-arm-kernel/cover/20240323231309.415425-1-martin.blumenstingl@googlemail.com/

To be continued!

Christian


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Re: [PATCH 2/2] iio: adc: meson: add support for the GXLX SoC

[Jonathan Cameron]

On Wed, 5 Jun 2024 07:15:58 +0400
Christian Hewitt <christianshewitt@gmail.com> wrote:

> > On 4 Jun 2024, at 1:10 PM, kernel test robot <lkp@intel.com> wrote:
> > 
> > kernel test robot noticed the following build errors:  
> 
> Apologies. Build errors are because I wrongly imagined this dependent series from Martin to be merged:
> 
> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20240323231309.415425-1-martin.blumenstingl@googlemail.com/
> 
> To be continued!
Given that was a case of not going to right mailing list, if you want
(and Martin doesn't have time) it is fine to pick that up and send it
a single series with your changes.

Thanks,

Jonathan

> 
> Christian
> 
> 


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Re: [PATCH 1/2] dt-bindings: iio: adc: amlogic,meson-saradc: add GXLX SoC compatible

[Jonathan Cameron]

On Tue,  4 Jun 2024 05:54:30 +0000
Christian Hewitt <christianshewitt@gmail.com> wrote:

> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> Add support for the GXLX SoC. GXLX is very similar to GXL but has three
> additional bits in MESON_SAR_ADC_REG12 for the three MPLL clocks.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
FWIW series looks fine to me subject to the precursor series getting
posted to linux-iio (and hence ending up in the right patchwork!)

Jonathan

> ---
>  .../devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
> index 7e8328e9ce13..b2fef72267b4 100644
> --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
> @@ -23,6 +23,7 @@ properties:
>                - amlogic,meson8m2-saradc
>                - amlogic,meson-gxbb-saradc
>                - amlogic,meson-gxl-saradc
> +              - amlogic,meson-gxlx-saradc
>                - amlogic,meson-gxm-saradc
>                - amlogic,meson-axg-saradc
>                - amlogic,meson-g12a-saradc


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