* [PATCH 1/4] mfd: stm32-timers: Unify alignment of register definition
2024-06-14 8:10 [PATCH 0/4] mfd: stm32-timers: Make register definition more flexible Uwe Kleine-König
@ 2024-06-14 8:10 ` Uwe Kleine-König
2024-06-18 17:46 ` Thorsten Scherer
2024-06-14 8:10 ` [PATCH 2/4] mfd: stm32-timers: Add some register definitions with a parameter Uwe Kleine-König
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Uwe Kleine-König @ 2024-06-14 8:10 UTC (permalink / raw)
To: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, Lee Jones
Cc: linux-iio, linux-pwm, linux-stm32, linux-arm-kernel, linux-kernel
Ust tabs consistently for indention and properly align register names,
values and comments. This improves readability (at least for my eyes).
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
include/linux/mfd/stm32-timers.h | 170 +++++++++++++++----------------
1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
index 9eb17481b07f..5794110b2b28 100644
--- a/include/linux/mfd/stm32-timers.h
+++ b/include/linux/mfd/stm32-timers.h
@@ -12,97 +12,97 @@
#include <linux/dma-mapping.h>
#include <linux/regmap.h>
-#define TIM_CR1 0x00 /* Control Register 1 */
-#define TIM_CR2 0x04 /* Control Register 2 */
-#define TIM_SMCR 0x08 /* Slave mode control reg */
-#define TIM_DIER 0x0C /* DMA/interrupt register */
-#define TIM_SR 0x10 /* Status register */
-#define TIM_EGR 0x14 /* Event Generation Reg */
-#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
-#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
-#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
-#define TIM_CNT 0x24 /* Counter */
-#define TIM_PSC 0x28 /* Prescaler */
-#define TIM_ARR 0x2c /* Auto-Reload Register */
-#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
-#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
-#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
-#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
-#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
-#define TIM_DCR 0x48 /* DMA control register */
-#define TIM_DMAR 0x4C /* DMA register for transfer */
-#define TIM_TISEL 0x68 /* Input Selection */
+#define TIM_CR1 0x00 /* Control Register 1 */
+#define TIM_CR2 0x04 /* Control Register 2 */
+#define TIM_SMCR 0x08 /* Slave mode control reg */
+#define TIM_DIER 0x0C /* DMA/interrupt register */
+#define TIM_SR 0x10 /* Status register */
+#define TIM_EGR 0x14 /* Event Generation Reg */
+#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
+#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
+#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
+#define TIM_CNT 0x24 /* Counter */
+#define TIM_PSC 0x28 /* Prescaler */
+#define TIM_ARR 0x2c /* Auto-Reload Register */
+#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
+#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
+#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
+#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
+#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
+#define TIM_DCR 0x48 /* DMA control register */
+#define TIM_DMAR 0x4C /* DMA register for transfer */
+#define TIM_TISEL 0x68 /* Input Selection */
-#define TIM_CR1_CEN BIT(0) /* Counter Enable */
-#define TIM_CR1_DIR BIT(4) /* Counter Direction */
-#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
-#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
-#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
-#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
-#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
-#define TIM_DIER_UIE BIT(0) /* Update interrupt */
-#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
-#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
-#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
-#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
-#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
-#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
-#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
-#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
-#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
-#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
-#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
-#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
-#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
-#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
-#define TIM_EGR_UG BIT(0) /* Update Generation */
-#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
-#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
-#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
-#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
-#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
-#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
-#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
-#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
-#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
-#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
-#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
-#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
-#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
-#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
-#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
-#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
-#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
-#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
-#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
-#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
-#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
-#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
-#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
-#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
-#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
-#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
-#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
-#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
-#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
-#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
-#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
-#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
-#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
-#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
-#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
+#define TIM_CR1_CEN BIT(0) /* Counter Enable */
+#define TIM_CR1_DIR BIT(4) /* Counter Direction */
+#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
+#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
+#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
+#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
+#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
+#define TIM_DIER_UIE BIT(0) /* Update interrupt */
+#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
+#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
+#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
+#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
+#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
+#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
+#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
+#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
+#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
+#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
+#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
+#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
+#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
+#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
+#define TIM_EGR_UG BIT(0) /* Update Generation */
+#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
+#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
+#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
+#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
+#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
+#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
+#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
+#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
+#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
+#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
+#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
+#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
+#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
+#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
+#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
+#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
+#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
+#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
+#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
+#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
+#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
+#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
+#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
+#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
+#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
+#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
+#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
+#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
+#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
+#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
+#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
+#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
+#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
+#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
+#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
-#define MAX_TIM_PSC 0xFFFF
-#define MAX_TIM_ICPSC 0x3
-#define TIM_CR2_MMS_SHIFT 4
-#define TIM_CR2_MMS2_SHIFT 20
+#define MAX_TIM_PSC 0xFFFF
+#define MAX_TIM_ICPSC 0x3
+#define TIM_CR2_MMS_SHIFT 4
+#define TIM_CR2_MMS2_SHIFT 20
#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */
#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */
#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */
#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */
-#define TIM_SMCR_TS_SHIFT 4
-#define TIM_BDTR_BKF_MASK 0xF
-#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
+#define TIM_SMCR_TS_SHIFT 4
+#define TIM_BDTR_BKF_MASK 0xF
+#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
enum stm32_timers_dmas {
STM32_TIMERS_DMA_CH1,
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 1/4] mfd: stm32-timers: Unify alignment of register definition
2024-06-14 8:10 ` [PATCH 1/4] mfd: stm32-timers: Unify alignment of register definition Uwe Kleine-König
@ 2024-06-18 17:46 ` Thorsten Scherer
0 siblings, 0 replies; 9+ messages in thread
From: Thorsten Scherer @ 2024-06-18 17:46 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, Lee Jones, linux-iio, linux-pwm, linux-stm32,
linux-arm-kernel, linux-kernel
Hi Uwe,
On Fri, Jun 14, 2024 at 10:10:11AM +0200, Uwe Kleine-König wrote:
> Ust tabs consistently for indention and properly align register names,
Litte typo here.
s/Ust/Use/
> values and comments. This improves readability (at least for my eyes).
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
> ---
> include/linux/mfd/stm32-timers.h | 170 +++++++++++++++----------------
> 1 file changed, 85 insertions(+), 85 deletions(-)
>
> diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
> index 9eb17481b07f..5794110b2b28 100644
> --- a/include/linux/mfd/stm32-timers.h
> +++ b/include/linux/mfd/stm32-timers.h
> @@ -12,97 +12,97 @@
> #include <linux/dma-mapping.h>
> #include <linux/regmap.h>
>
> -#define TIM_CR1 0x00 /* Control Register 1 */
> -#define TIM_CR2 0x04 /* Control Register 2 */
> -#define TIM_SMCR 0x08 /* Slave mode control reg */
> -#define TIM_DIER 0x0C /* DMA/interrupt register */
> -#define TIM_SR 0x10 /* Status register */
> -#define TIM_EGR 0x14 /* Event Generation Reg */
> -#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> -#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> -#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> -#define TIM_CNT 0x24 /* Counter */
> -#define TIM_PSC 0x28 /* Prescaler */
> -#define TIM_ARR 0x2c /* Auto-Reload Register */
> -#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> -#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> -#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> -#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> -#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> -#define TIM_DCR 0x48 /* DMA control register */
> -#define TIM_DMAR 0x4C /* DMA register for transfer */
> -#define TIM_TISEL 0x68 /* Input Selection */
> +#define TIM_CR1 0x00 /* Control Register 1 */
> +#define TIM_CR2 0x04 /* Control Register 2 */
> +#define TIM_SMCR 0x08 /* Slave mode control reg */
> +#define TIM_DIER 0x0C /* DMA/interrupt register */
> +#define TIM_SR 0x10 /* Status register */
> +#define TIM_EGR 0x14 /* Event Generation Reg */
> +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> +#define TIM_CNT 0x24 /* Counter */
> +#define TIM_PSC 0x28 /* Prescaler */
> +#define TIM_ARR 0x2c /* Auto-Reload Register */
> +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> +#define TIM_DCR 0x48 /* DMA control register */
> +#define TIM_DMAR 0x4C /* DMA register for transfer */
> +#define TIM_TISEL 0x68 /* Input Selection */
>
> -#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> -#define TIM_CR1_DIR BIT(4) /* Counter Direction */
> -#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> -#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> -#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
> -#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> -#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> -#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> -#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
> -#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
> -#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
> -#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
> -#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
> -#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
> -#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
> -#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
> -#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
> -#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
> -#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
> -#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
> -#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> -#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
> -#define TIM_EGR_UG BIT(0) /* Update Generation */
> -#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> -#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> -#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
> -#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
> -#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
> -#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
> -#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
> -#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
> -#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
> -#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
> -#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
> -#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
> -#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
> -#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
> -#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> -#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> -#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> -#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> -#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
> -#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
> -#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
> -#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
> -#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
> -#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
> -#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
> -#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
> -#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
> -#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> -#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
> -#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
> -#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> -#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> -#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
> -#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
> -#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
> +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> +#define TIM_CR1_DIR BIT(4) /* Counter Direction */
> +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
> +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> +#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
> +#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
> +#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
> +#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
> +#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
> +#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
> +#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
> +#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
> +#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
> +#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
> +#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
> +#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
> +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
> +#define TIM_EGR_UG BIT(0) /* Update Generation */
> +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> +#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
> +#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
> +#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
> +#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
> +#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
> +#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
> +#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
> +#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
> +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
> +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
> +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
> +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
> +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> +#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
> +#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
> +#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
> +#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
> +#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
> +#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
> +#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
> +#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
> +#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
> +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> +#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
> +#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
> +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> +#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
> +#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
> +#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
>
> -#define MAX_TIM_PSC 0xFFFF
> -#define MAX_TIM_ICPSC 0x3
> -#define TIM_CR2_MMS_SHIFT 4
> -#define TIM_CR2_MMS2_SHIFT 20
> +#define MAX_TIM_PSC 0xFFFF
> +#define MAX_TIM_ICPSC 0x3
> +#define TIM_CR2_MMS_SHIFT 4
> +#define TIM_CR2_MMS2_SHIFT 20
> #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */
> #define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */
> #define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */
> #define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */
> -#define TIM_SMCR_TS_SHIFT 4
> -#define TIM_BDTR_BKF_MASK 0xF
> -#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
> +#define TIM_SMCR_TS_SHIFT 4
> +#define TIM_BDTR_BKF_MASK 0xF
> +#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
>
> enum stm32_timers_dmas {
> STM32_TIMERS_DMA_CH1,
> --
> 2.43.0
>
>
Best regards
Thorsten
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] mfd: stm32-timers: Add some register definitions with a parameter
2024-06-14 8:10 [PATCH 0/4] mfd: stm32-timers: Make register definition more flexible Uwe Kleine-König
2024-06-14 8:10 ` [PATCH 1/4] mfd: stm32-timers: Unify alignment of register definition Uwe Kleine-König
@ 2024-06-14 8:10 ` Uwe Kleine-König
2024-06-14 8:10 ` [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x) Uwe Kleine-König
2024-06-14 8:10 ` [PATCH 4/4] pwm-stm32: Make use of parametrised register definitions Uwe Kleine-König
3 siblings, 0 replies; 9+ messages in thread
From: Uwe Kleine-König @ 2024-06-14 8:10 UTC (permalink / raw)
To: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, Lee Jones
Cc: linux-iio, linux-pwm, linux-stm32, linux-arm-kernel, linux-kernel
There are some registers that belong together and are numbered from 1 to
4. Introduce a macro definition for these that takes the channel number
as parameter and define the previously available constants using the new
ones.
This allows to simplify some users that up to now use constructs like
TIM_CCER_CC1NE << (ch * 4)
which is an ugly mix of using a predefined value and still knowing
internal details about it.
Note that there are several decrements by 1 involved. These are
necessary because software guys start counting at 0 while the hardware
designer started at 1 (and having TIM_CCER_CCxE(1) be TIM_CCER_CC2E
isn't a sane option). The compiler is expected to optimize these out
nicely.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
include/linux/mfd/stm32-timers.h | 60 +++++++++++++++++++-------------
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
index 5794110b2b28..92b45a559656 100644
--- a/include/linux/mfd/stm32-timers.h
+++ b/include/linux/mfd/stm32-timers.h
@@ -24,10 +24,11 @@
#define TIM_CNT 0x24 /* Counter */
#define TIM_PSC 0x28 /* Prescaler */
#define TIM_ARR 0x2c /* Auto-Reload Register */
-#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
-#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
-#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
-#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
+#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */
+#define TIM_CCR1 TIM_CCRx(1) /* Capt/Comp Register 1 */
+#define TIM_CCR2 TIM_CCRx(2) /* Capt/Comp Register 2 */
+#define TIM_CCR3 TIM_CCRx(3) /* Capt/Comp Register 3 */
+#define TIM_CCR4 TIM_CCRx(4) /* Capt/Comp Register 4 */
#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
#define TIM_DCR 0x48 /* DMA control register */
#define TIM_DMAR 0x4C /* DMA register for transfer */
@@ -41,16 +42,18 @@
#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
#define TIM_DIER_UIE BIT(0) /* Update interrupt */
-#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
-#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
-#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
-#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
+#define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */
+#define TIM_DIER_CC1IE TIM_DIER_CCxIE(1) /* CC1 Interrupt Enable */
+#define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */
+#define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */
+#define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */
#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
-#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
-#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
-#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
-#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
+#define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */
+#define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */
+#define TIM_DIER_CC2DE TIM_DIER_CCxDE(2) /* CC2 DMA request Enable */
+#define TIM_DIER_CC3DE TIM_DIER_CCxDE(3) /* CC3 DMA request Enable */
+#define TIM_DIER_CC4DE TIM_DIER_CCxDE(4) /* CC4 DMA request Enable */
#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
@@ -70,19 +73,26 @@
#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
-#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
-#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
-#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
-#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
-#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
-#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
-#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
-#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
-#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
-#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
-#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
-#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
-#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
+#define TIM_CCER_CCxE(x) BIT(0 + 4 * ((x) - 1)) /* Capt/Comp x out Ena (x ∈ {1, .. 4}) */
+#define TIM_CCER_CCxP(x) BIT(1 + 4 * ((x) - 1)) /* Capt/Comp x Polarity (x ∈ {1, .. 4}) */
+#define TIM_CCER_CCxNE(x) BIT(2 + 4 * ((x) - 1)) /* Capt/Comp xN out Ena (x ∈ {1, .. 4}) */
+#define TIM_CCER_CCxNP(x) BIT(3 + 4 * ((x) - 1)) /* Capt/Comp xN Polarity (x ∈ {1, .. 4}) */
+#define TIM_CCER_CC1E TIM_CCER_CCxE(1) /* Capt/Comp 1 out Ena */
+#define TIM_CCER_CC1P TIM_CCER_CCxP(1) /* Capt/Comp 1 Polarity */
+#define TIM_CCER_CC1NE TIM_CCER_CCxNE(1) /* Capt/Comp 1N out Ena */
+#define TIM_CCER_CC1NP TIM_CCER_CCxNP(1) /* Capt/Comp 1N Polarity */
+#define TIM_CCER_CC2E TIM_CCER_CCxE(2) /* Capt/Comp 2 out Ena */
+#define TIM_CCER_CC2P TIM_CCER_CCxP(2) /* Capt/Comp 2 Polarity */
+#define TIM_CCER_CC2NE TIM_CCER_CCxNE(2) /* Capt/Comp 2N out Ena */
+#define TIM_CCER_CC2NP TIM_CCER_CCxNP(2) /* Capt/Comp 2N Polarity */
+#define TIM_CCER_CC3E TIM_CCER_CCxE(3) /* Capt/Comp 3 out Ena */
+#define TIM_CCER_CC3P TIM_CCER_CCxP(3) /* Capt/Comp 3 Polarity */
+#define TIM_CCER_CC3NE TIM_CCER_CCxNE(3) /* Capt/Comp 3N out Ena */
+#define TIM_CCER_CC3NP TIM_CCER_CCxNP(3) /* Capt/Comp 3N Polarity */
+#define TIM_CCER_CC4E TIM_CCER_CCxE(4) /* Capt/Comp 4 out Ena */
+#define TIM_CCER_CC4P TIM_CCER_CCxP(4) /* Capt/Comp 4 Polarity */
+#define TIM_CCER_CC4NE TIM_CCER_CCxNE(4) /* Capt/Comp 4N out Ena */
+#define TIM_CCER_CC4NP TIM_CCER_CCxNP(4) /* Capt/Comp 4N Polarity */
#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x)
2024-06-14 8:10 [PATCH 0/4] mfd: stm32-timers: Make register definition more flexible Uwe Kleine-König
2024-06-14 8:10 ` [PATCH 1/4] mfd: stm32-timers: Unify alignment of register definition Uwe Kleine-König
2024-06-14 8:10 ` [PATCH 2/4] mfd: stm32-timers: Add some register definitions with a parameter Uwe Kleine-König
@ 2024-06-14 8:10 ` Uwe Kleine-König
2024-06-14 9:31 ` Lee Jones
2024-06-16 8:46 ` William Breathitt Gray
2024-06-14 8:10 ` [PATCH 4/4] pwm-stm32: Make use of parametrised register definitions Uwe Kleine-König
3 siblings, 2 replies; 9+ messages in thread
From: Uwe Kleine-König @ 2024-06-14 8:10 UTC (permalink / raw)
To: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, Lee Jones
Cc: linux-iio, linux-pwm, linux-stm32, linux-arm-kernel, linux-kernel
These two defines have the same purpose and this change doesn't
introduce any differences in drivers/counter/stm32-timer-cnt.o.
The only difference between the two is that
TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE
while
TIM_DIER_CCxIE(1) == TIM_DIER_CC1IE
. That makes it necessary to have an explicit "+ 1" in the user code,
but IMHO this is a good thing as this is the code locatation that
"knows" that for software channel 1 you have to use TIM_DIER_CC2IE
(because software guys start counting at 0, while the relevant hardware
designer started at 1).
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
drivers/counter/stm32-timer-cnt.c | 4 ++--
include/linux/mfd/stm32-timers.h | 1 -
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
index 0664ef969f79..186e73d6ccb4 100644
--- a/drivers/counter/stm32-timer-cnt.c
+++ b/drivers/counter/stm32-timer-cnt.c
@@ -465,7 +465,7 @@ static int stm32_count_events_configure(struct counter_device *counter)
ret = stm32_count_capture_configure(counter, event_node->channel, true);
if (ret)
return ret;
- dier |= TIM_DIER_CC_IE(event_node->channel);
+ dier |= TIM_DIER_CCxIE(event_node->channel + 1);
break;
default:
/* should never reach this path */
@@ -478,7 +478,7 @@ static int stm32_count_events_configure(struct counter_device *counter)
/* check for disabled capture events */
for (i = 0 ; i < priv->nchannels; i++) {
- if (!(dier & TIM_DIER_CC_IE(i))) {
+ if (!(dier & TIM_DIER_CCxIE(i + 1))) {
ret = stm32_count_capture_configure(counter, i, false);
if (ret)
return ret;
diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
index 92b45a559656..f09ba598c97a 100644
--- a/include/linux/mfd/stm32-timers.h
+++ b/include/linux/mfd/stm32-timers.h
@@ -47,7 +47,6 @@
#define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */
#define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */
#define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */
-#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
#define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */
#define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x)
2024-06-14 8:10 ` [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x) Uwe Kleine-König
@ 2024-06-14 9:31 ` Lee Jones
2024-06-16 13:52 ` Uwe Kleine-König
2024-06-16 8:46 ` William Breathitt Gray
1 sibling, 1 reply; 9+ messages in thread
From: Lee Jones @ 2024-06-14 9:31 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, linux-iio, linux-pwm, linux-stm32,
linux-arm-kernel, linux-kernel
On Fri, 14 Jun 2024, Uwe Kleine-König wrote:
> These two defines have the same purpose and this change doesn't
> introduce any differences in drivers/counter/stm32-timer-cnt.o.
>
> The only difference between the two is that
>
> TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE
>
> while
>
> TIM_DIER_CCxIE(1) == TIM_DIER_CC1IE
>
> . That makes it necessary to have an explicit "+ 1" in the user code,
> but IMHO this is a good thing as this is the code locatation that
> "knows" that for software channel 1 you have to use TIM_DIER_CC2IE
> (because software guys start counting at 0, while the relevant hardware
> designer started at 1).
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
> ---
> drivers/counter/stm32-timer-cnt.c | 4 ++--
The subject should be renamed.
> include/linux/mfd/stm32-timers.h | 1 -
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
> index 0664ef969f79..186e73d6ccb4 100644
> --- a/drivers/counter/stm32-timer-cnt.c
> +++ b/drivers/counter/stm32-timer-cnt.c
> @@ -465,7 +465,7 @@ static int stm32_count_events_configure(struct counter_device *counter)
> ret = stm32_count_capture_configure(counter, event_node->channel, true);
> if (ret)
> return ret;
> - dier |= TIM_DIER_CC_IE(event_node->channel);
> + dier |= TIM_DIER_CCxIE(event_node->channel + 1);
> break;
> default:
> /* should never reach this path */
> @@ -478,7 +478,7 @@ static int stm32_count_events_configure(struct counter_device *counter)
>
> /* check for disabled capture events */
> for (i = 0 ; i < priv->nchannels; i++) {
> - if (!(dier & TIM_DIER_CC_IE(i))) {
> + if (!(dier & TIM_DIER_CCxIE(i + 1))) {
> ret = stm32_count_capture_configure(counter, i, false);
> if (ret)
> return ret;
> diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
> index 92b45a559656..f09ba598c97a 100644
> --- a/include/linux/mfd/stm32-timers.h
> +++ b/include/linux/mfd/stm32-timers.h
> @@ -47,7 +47,6 @@
> #define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */
> #define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */
> #define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */
> -#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
> #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
> #define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */
> #define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */
> --
> 2.43.0
>
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x)
2024-06-14 9:31 ` Lee Jones
@ 2024-06-16 13:52 ` Uwe Kleine-König
0 siblings, 0 replies; 9+ messages in thread
From: Uwe Kleine-König @ 2024-06-16 13:52 UTC (permalink / raw)
To: Lee Jones
Cc: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, linux-iio, linux-pwm, linux-stm32,
linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1095 bytes --]
Hello Lee,
On Fri, Jun 14, 2024 at 10:31:24AM +0100, Lee Jones wrote:
> On Fri, 14 Jun 2024, Uwe Kleine-König wrote:
>
> > These two defines have the same purpose and this change doesn't
> > introduce any differences in drivers/counter/stm32-timer-cnt.o.
> >
> > The only difference between the two is that
> >
> > TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE
> >
> > while
> >
> > TIM_DIER_CCxIE(1) == TIM_DIER_CC1IE
> >
> > . That makes it necessary to have an explicit "+ 1" in the user code,
> > but IMHO this is a good thing as this is the code locatation that
> > "knows" that for software channel 1 you have to use TIM_DIER_CC2IE
> > (because software guys start counting at 0, while the relevant hardware
> > designer started at 1).
> >
> > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
> > ---
> > drivers/counter/stm32-timer-cnt.c | 4 ++--
>
> The subject should be renamed.
I guess you mean it should be something like:
counter: stm32-timer-cnt: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x + 1)
?
Best regards
Uwe
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x)
2024-06-14 8:10 ` [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x) Uwe Kleine-König
2024-06-14 9:31 ` Lee Jones
@ 2024-06-16 8:46 ` William Breathitt Gray
1 sibling, 0 replies; 9+ messages in thread
From: William Breathitt Gray @ 2024-06-16 8:46 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabrice Gasnier, Maxime Coquelin, Alexandre Torgue, Lee Jones,
linux-iio, linux-pwm, linux-stm32, linux-arm-kernel, linux-kernel
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On Fri, Jun 14, 2024 at 10:10:13AM +0200, Uwe Kleine-König wrote:
> These two defines have the same purpose and this change doesn't
> introduce any differences in drivers/counter/stm32-timer-cnt.o.
>
> The only difference between the two is that
>
> TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE
>
> while
>
> TIM_DIER_CCxIE(1) == TIM_DIER_CC1IE
>
> . That makes it necessary to have an explicit "+ 1" in the user code,
> but IMHO this is a good thing as this is the code locatation that
> "knows" that for software channel 1 you have to use TIM_DIER_CC2IE
> (because software guys start counting at 0, while the relevant hardware
> designer started at 1).
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
I concur with Lee Jones that the subject should be renamed. Regardless,
here's my ack for the code changes.
Acked-by: William Breathitt Gray <wbg@kernel.org>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] pwm-stm32: Make use of parametrised register definitions
2024-06-14 8:10 [PATCH 0/4] mfd: stm32-timers: Make register definition more flexible Uwe Kleine-König
` (2 preceding siblings ...)
2024-06-14 8:10 ` [PATCH 3/4] mfd: stm32-timers: Drop TIM_DIER_CC_IE(x) in favour of TIM_DIER_CCxIE(x) Uwe Kleine-König
@ 2024-06-14 8:10 ` Uwe Kleine-König
3 siblings, 0 replies; 9+ messages in thread
From: Uwe Kleine-König @ 2024-06-14 8:10 UTC (permalink / raw)
To: Fabrice Gasnier, William Breathitt Gray, Maxime Coquelin,
Alexandre Torgue, Lee Jones
Cc: linux-iio, linux-pwm, linux-stm32, linux-arm-kernel, linux-kernel
There is no semantic change, but it is a nicer on the eyes of a reader,
because
TIM_CCR1 + 4 * ch
encodes internal register knowledge, while
TIM_CCRx(ch + 1)
keeps that information completely in the header defining the registers.
While I expected this to not result in any changes in the binary, gcc 13
(as provided by Debian in the gcc-13-arm-linux-gnueabihf 13.2.0-12cross1
package) compiles the new version with an allmodconfig to more compact
code:
$ source/scripts/bloat-o-meter drivers/pwm/pwm-stm32.o-pre drivers/pwm/pwm-stm32.o
add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-488 (-488)
Function old new delta
stm32_pwm_get_state 968 936 -32
stm32_pwm_apply_locked 1920 1464 -456
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
---
drivers/pwm/pwm-stm32.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
index a2f231d13a9f..49a76514b83e 100644
--- a/drivers/pwm/pwm-stm32.c
+++ b/drivers/pwm/pwm-stm32.c
@@ -360,7 +360,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),
(u64)NSEC_PER_SEC * (prescaler + 1));
- regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
+ regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty);
/* Configure output mode */
shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
@@ -382,9 +382,9 @@ static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
{
u32 mask;
- mask = TIM_CCER_CC1P << (ch * 4);
+ mask = TIM_CCER_CCxP(ch + 1);
if (priv->have_complementary_output)
- mask |= TIM_CCER_CC1NP << (ch * 4);
+ mask |= TIM_CCER_CCxNP(ch + 1);
regmap_update_bits(priv->regmap, TIM_CCER, mask,
polarity == PWM_POLARITY_NORMAL ? 0 : mask);
@@ -402,9 +402,9 @@ static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
return ret;
/* Enable channel */
- mask = TIM_CCER_CC1E << (ch * 4);
+ mask = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
- mask |= TIM_CCER_CC1NE << (ch * 4);
+ mask |= TIM_CCER_CCxNE(ch);
regmap_set_bits(priv->regmap, TIM_CCER, mask);
@@ -422,9 +422,9 @@ static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
u32 mask;
/* Disable channel */
- mask = TIM_CCER_CC1E << (ch * 4);
+ mask = TIM_CCER_CCxE(ch + 1);
if (priv->have_complementary_output)
- mask |= TIM_CCER_CC1NE << (ch * 4);
+ mask |= TIM_CCER_CCxNE(ch + 1);
regmap_clear_bits(priv->regmap, TIM_CCER, mask);
@@ -493,8 +493,8 @@ static int stm32_pwm_get_state(struct pwm_chip *chip,
if (ret)
goto out;
- state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4));
- state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ?
+ state->enabled = ccer & TIM_CCER_CCxE(ch + 1);
+ state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ?
PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
ret = regmap_read(priv->regmap, TIM_PSC, &psc);
if (ret)
@@ -502,7 +502,7 @@ static int stm32_pwm_get_state(struct pwm_chip *chip,
ret = regmap_read(priv->regmap, TIM_ARR, &arr);
if (ret)
goto out;
- ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr);
+ ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr);
if (ret)
goto out;
@@ -702,7 +702,7 @@ static int stm32_pwm_suspend(struct device *dev)
ccer = active_channels(priv);
for (i = 0; i < chip->npwm; i++) {
- mask = TIM_CCER_CC1E << (i * 4);
+ mask = TIM_CCER_CCxE(i + 1);
if (ccer & mask) {
dev_err(dev, "PWM %u still in use by consumer %s\n",
i, chip->pwms[i].label);
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread