From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1771C2BA18 for ; Mon, 17 Jun 2024 16:46:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=775Rc3YSZJA9GkF9P0glZgOGiZ3l+SlVgXxf6vD2zUg=; b=VJwHMNkAYABP91fTeMcpTDUrmg ju2T1xaYCt4ByoOq19Tx8ZNcurU4na1YlFU+xXs8RYaOl7atKe7ZuGG2E6oUiMa8LT/x6vn47MZsC SvG17D3pLgguXzVc9VJgXFnmm/pu742JGUmH1rX/gjgaxNUzXsdhX3T332DrCFU54vZBlvngjylZA nXkJRMm8ZtjaFcbXA2V1SEZAfVm/FSgI6XSjcZYFjh1YeEhqUyaCjpDxAL4fe7lGDCk5Q5tumpydI XZ3VWwr+Cz7VoH9WwCvSwPjEijS9C/5tTRSbcNAVnVG7tE4bmhvTBcuxMC7m3YxVp9Bwy3epIIm3S 6Lg0Rluw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJFUs-0000000Bngq-0pK9; Mon, 17 Jun 2024 16:46:22 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJFTn-0000000Bn1J-1Weo for linux-arm-kernel@lists.infradead.org; Mon, 17 Jun 2024 16:45:22 +0000 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a6269885572so958030466b.1 for ; Mon, 17 Jun 2024 09:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1718642713; x=1719247513; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=775Rc3YSZJA9GkF9P0glZgOGiZ3l+SlVgXxf6vD2zUg=; b=jSIjn0MQSjMG+Ip3gqd1eoClv/NABwlYH7d/FdJot485v3gLYKbGP2n2r4DimOv84B 78ES08VuSyA05BR9Hg0SieP37EPHTNNlujQx64vqJ7q17skGDPJK+dnR/DPjEELEwlZA w0J8pE5vBptdj151J+oK+pS+jF0oQjh0fQjMkyYmi5DAs0ztp8ndGRuRWuma//vdM6MN vxbfiNi15gg8kJpSuY31XPs8ikUK0QmMKjXW/3Q/07UOpxWyCJEk3L2fVPcxjQKI4TTs ZwjjzcUSSUM96jmk2jJZldy9rezaRAplQJqcGNd2M6dp45lw0bDKug6KRo27HSHiO6YM auPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718642713; x=1719247513; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=775Rc3YSZJA9GkF9P0glZgOGiZ3l+SlVgXxf6vD2zUg=; b=CS94SrhTihtUPKe23dWBpMx+MhnjjQvv+hh3lGxRbRoiWjLxy7ZXwn1fX6C10RKu2C mJTLh2Vgm7NN736WeDA22ZsNY9tzwt3UTt5SRp8AiKj28/zdRDMue0e+dTCvcAHVQdJV vmM2CDDe6QnnMYhyLJnCPA/OiLTseFM5sNedxOVv59tjSvhJxw47Ce8RgwUG7l5GlvIY PbKsQD0pgxhkRoI95p8GcNyIR1pAabZY+NCEq6/FiaPNGxUnHXYQ3/2H8hFb6pGD75SJ u2SkFGuVJ1HivHec5hguOd2A9wGbCO4tuYbkX9Kj8v528Ei0eoSFYTAewJk0vym5redx JRMA== X-Forwarded-Encrypted: i=1; AJvYcCUjwwtIIWTxRjD6VpACju0jD5L9sDlClpFdgcxj3urhlHD2QMz+6Z4ppVDJ1CL9FDaSdcMnGflIPlz6rmHKG0tcuCd3wL72Eb0UCuBuSw+/GkVXhSM= X-Gm-Message-State: AOJu0YzjT+w4tcnYjtNO41EMJ4Auzqlm6fFKchiod8bSYCkm4nx5jt1W 9qOisumqs4UXv9UUczZ9ExkL91XHyawtbclOA1cD7SAnz1+Y70v7yAE4JBL+2i8= X-Google-Smtp-Source: AGHT+IGxghexs1XqxhT5potawbeFSAX16ipohQs+SrpdF0FJ0NKfLsTElkU4lhVhPvf7HZsnVf1r1Q== X-Received: by 2002:a17:906:ba89:b0:a6f:6960:5e15 with SMTP id a640c23a62f3a-a6f94c13e0emr12835266b.7.1718642713131; Mon, 17 Jun 2024 09:45:13 -0700 (PDT) Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com. [35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f56f4170bsm527139966b.157.2024.06.17.09.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 09:45:12 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 17 Jun 2024 17:44:45 +0100 Subject: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org> References: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org> In-Reply-To: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar , Sam Protsenko Cc: Krzysztof Kozlowski , Tudor Ambarus , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_094515_648111_32EA5383 X-CRM114-Status: GOOD ( 17.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In preparation for support for additional platforms, convert the phy register access clock to using the clk_bulk interfaces. Newer SoCs like Google Tensor gs101 require additional clocks for access to additional (different) register areas (PHY, PMA, PCS), and converting to clk_bulk simplifies addition of those extra clocks. Signed-off-by: André Draszik --- v3: * make the register access clock name(s) platform specific and avoid use of devm_clk_bulk_get_optional() as we want to be sure to have retrieved all required clocks * fix a whitespace issue * slightly rephrase commit message --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 54 +++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 35b307dad2ee..80a3891fd605 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -185,6 +185,8 @@ struct exynos5_usbdrd_phy_config { struct exynos5_usbdrd_phy_drvdata { const struct exynos5_usbdrd_phy_config *phy_cfg; const struct phy_ops *phy_ops; + const char * const *clk_names; + int n_clks; const char * const *core_clk_names; int n_core_clks; u32 pmu_offset_usbdrd0_phy; @@ -196,7 +198,7 @@ struct exynos5_usbdrd_phy_drvdata { * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY * @dev: pointer to device instance of this platform device * @reg_phy: usb phy controller register memory base - * @clk: phy clock for register access + * @clks: clocks for register access * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required) * @drv_data: pointer to SoC level driver data structure * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY @@ -209,7 +211,7 @@ struct exynos5_usbdrd_phy_drvdata { struct exynos5_usbdrd_phy { struct device *dev; void __iomem *reg_phy; - struct clk *clk; + struct clk_bulk_data *clks; struct clk_bulk_data *core_clks; const struct exynos5_usbdrd_phy_drvdata *drv_data; struct phy_usb_instance { @@ -402,7 +404,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) struct phy_usb_instance *inst = phy_get_drvdata(phy); struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); - ret = clk_prepare_enable(phy_drd->clk); + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); if (ret) return ret; @@ -452,7 +454,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) reg &= ~PHYCLKRST_PORTRESET; writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); - clk_disable_unprepare(phy_drd->clk); + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } @@ -464,7 +466,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy) struct phy_usb_instance *inst = phy_get_drvdata(phy); struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); - ret = clk_prepare_enable(phy_drd->clk); + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); if (ret) return ret; @@ -486,7 +488,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy) PHYTEST_POWERDOWN_HSP; writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); - clk_disable_unprepare(phy_drd->clk); + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } @@ -811,14 +813,14 @@ static int exynos850_usbdrd_phy_init(struct phy *phy) struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); int ret; - ret = clk_prepare_enable(phy_drd->clk); + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); if (ret) return ret; /* UTMI or PIPE3 specific init */ inst->phy_cfg->phy_init(phy_drd); - clk_disable_unprepare(phy_drd->clk); + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } @@ -831,7 +833,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) u32 reg; int ret; - ret = clk_prepare_enable(phy_drd->clk); + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); if (ret) return ret; @@ -854,7 +856,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) reg &= ~CLKRST_LINK_SW_RST; writel(reg, regs_base + EXYNOS850_DRD_CLKRST); - clk_disable_unprepare(phy_drd->clk); + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } @@ -873,11 +875,19 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd) struct clk *ref_clk; unsigned long ref_rate; - phy_drd->clk = devm_clk_get(phy_drd->dev, "phy"); - if (IS_ERR(phy_drd->clk)) { - dev_err(phy_drd->dev, "Failed to get phy clock\n"); - return PTR_ERR(phy_drd->clk); - } + phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks, + sizeof(*phy_drd->clks), GFP_KERNEL); + if (!phy_drd->clks) + return -ENOMEM; + + for (int i = 0; i < phy_drd->drv_data->n_clks; ++i) + phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i]; + + ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks, + phy_drd->clks); + if (ret) + return dev_err_probe(phy_drd->dev, ret, + "failed to get phy clock(s)\n"); phy_drd->core_clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_core_clks, @@ -939,6 +949,10 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = { }, }; +static const char * const exynos5_clk_names[] = { + "phy", +}; + static const char * const exynos5_core_clk_names[] = { "ref", }; @@ -952,6 +966,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), .core_clk_names = exynos5_core_clk_names, .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), }; @@ -960,6 +976,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), .core_clk_names = exynos5_core_clk_names, .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), }; @@ -969,6 +987,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = { .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), .core_clk_names = exynos5433_core_clk_names, .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names), }; @@ -977,6 +997,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), .core_clk_names = exynos5433_core_clk_names, .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names), }; @@ -985,6 +1007,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { .phy_cfg = phy_cfg_exynos850, .phy_ops = &exynos850_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), .core_clk_names = exynos5_core_clk_names, .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), }; -- 2.45.2.627.g7a2c4fd464-goog