* [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function [not found] <20240618164133.223194-1-linux.amoon@gmail.com> @ 2024-06-18 16:41 ` Anand Moon 2024-06-20 0:54 ` kernel test robot 2024-06-20 17:31 ` kernel test robot 2024-06-18 16:41 ` [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Anand Moon 2024-06-18 16:41 ` [PATCH v1 3/3] PCI: rockchip: refactor rockchip_pcie_disable_clocks function signature Anand Moon 2 siblings, 2 replies; 7+ messages in thread From: Anand Moon @ 2024-06-18 16:41 UTC (permalink / raw) To: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner Cc: Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Refactors the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- drivers/pci/controller/pcie-rockchip.c | 64 ++++---------------------- drivers/pci/controller/pcie-rockchip.h | 14 ++++-- 2 files changed, 20 insertions(+), 58 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 0ef2e622d36e..166dad666a35 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) struct platform_device *pdev = to_platform_device(dev); struct device_node *node = dev->of_node; struct resource *regs; - int err; + int err, i; if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev, @@ -127,28 +127,13 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) "failed to get ep GPIO\n"); } - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); - if (IS_ERR(rockchip->aclk_pcie)) { - dev_err(dev, "aclk clock not found\n"); - return PTR_ERR(rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); - if (IS_ERR(rockchip->aclk_perf_pcie)) { - dev_err(dev, "aclk_perf clock not found\n"); - return PTR_ERR(rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); - if (IS_ERR(rockchip->hclk_pcie)) { - dev_err(dev, "hclk clock not found\n"); - return PTR_ERR(rockchip->hclk_pcie); - } + for (i = 0; i < ROCKCHIP_NUM_CLKS; i++) + rockchip->clks[i].id = rockchip_pci_clks[i]; - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); - if (IS_ERR(rockchip->clk_pcie_pm)) { - dev_err(dev, "pm clock not found\n"); - return PTR_ERR(rockchip->clk_pcie_pm); + err = devm_clk_bulk_get(dev, ROCKCHIP_NUM_CLKS, rockchip->clks); + if (err) { + dev_err(dev, "rockchip clk bulk get failed\n"); + return err; } return 0; @@ -372,39 +357,13 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) struct device *dev = rockchip->dev; int err; - err = clk_prepare_enable(rockchip->aclk_pcie); + err = clk_bulk_prepare_enable(ROCKCHIP_NUM_CLKS, rockchip->clks); if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); + dev_err(dev, "rockchip clk bulk prepare enable failed\n"); return err; } - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); - goto err_clk_pcie_pm; - } - return 0; - -err_clk_pcie_pm: - clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: - clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: - clk_disable_unprepare(rockchip->aclk_pcie); - return err; } EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); @@ -412,10 +371,7 @@ void rockchip_pcie_disable_clocks(void *data) { struct rockchip_pcie *rockchip = data; - clk_disable_unprepare(rockchip->clk_pcie_pm); - clk_disable_unprepare(rockchip->hclk_pcie); - clk_disable_unprepare(rockchip->aclk_perf_pcie); - clk_disable_unprepare(rockchip->aclk_pcie); + clk_bulk_disable_unprepare(ROCKCHIP_NUM_CLKS, rockchip->clks); } EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 6111de35f84c..f256cdf4fa49 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -287,6 +287,15 @@ (((c) << ((b) * 8 + 5)) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_CLKS ARRAY_SIZE(rockchip_pci_clks) + +static const char * const rockchip_pci_clks[] = { + "aclk", + "aclk-perf", + "hclk", + "pm", +}; + struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ @@ -299,10 +308,7 @@ struct rockchip_pcie { struct reset_control *pm_rst; struct reset_control *aclk_rst; struct reset_control *pclk_rst; - struct clk *aclk_pcie; - struct clk *aclk_perf_pcie; - struct clk *hclk_pcie; - struct clk *clk_pcie_pm; + struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; struct regulator *vpcie12v; /* 12V power supply */ struct regulator *vpcie3v3; /* 3.3V power supply */ struct regulator *vpcie1v8; /* 1.8V power supply */ -- 2.44.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function 2024-06-18 16:41 ` [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon @ 2024-06-20 0:54 ` kernel test robot 2024-06-20 2:15 ` Anand Moon 2024-06-20 17:31 ` kernel test robot 1 sibling, 1 reply; 7+ messages in thread From: kernel test robot @ 2024-06-20 0:54 UTC (permalink / raw) To: Anand Moon, Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner Cc: oe-kbuild-all, Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Hi Anand, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/config) compiler: arceb-elf-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406200818.CQ7DXNSZ-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: >> drivers/pci/controller/pcie-rockchip.h:311:31: error: array type has incomplete element type 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^~~~ vim +311 drivers/pci/controller/pcie-rockchip.h 298 299 struct rockchip_pcie { 300 void __iomem *reg_base; /* DT axi-base */ 301 void __iomem *apb_base; /* DT apb-base */ 302 bool legacy_phy; 303 struct phy *phys[MAX_LANE_NUM]; 304 struct reset_control *core_rst; 305 struct reset_control *mgmt_rst; 306 struct reset_control *mgmt_sticky_rst; 307 struct reset_control *pipe_rst; 308 struct reset_control *pm_rst; 309 struct reset_control *aclk_rst; 310 struct reset_control *pclk_rst; > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; 312 struct regulator *vpcie12v; /* 12V power supply */ 313 struct regulator *vpcie3v3; /* 3.3V power supply */ 314 struct regulator *vpcie1v8; /* 1.8V power supply */ 315 struct regulator *vpcie0v9; /* 0.9V power supply */ 316 struct gpio_desc *ep_gpio; 317 u32 lanes; 318 u8 lanes_map; 319 int link_gen; 320 struct device *dev; 321 struct irq_domain *irq_domain; 322 int offset; 323 void __iomem *msg_region; 324 phys_addr_t msg_bus_addr; 325 bool is_rc; 326 struct resource *mem_res; 327 }; 328 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function 2024-06-20 0:54 ` kernel test robot @ 2024-06-20 2:15 ` Anand Moon 0 siblings, 0 replies; 7+ messages in thread From: Anand Moon @ 2024-06-20 2:15 UTC (permalink / raw) To: kernel test robot Cc: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner, oe-kbuild-all, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Hi All, On Thu, 20 Jun 2024 at 06:25, kernel test robot <lkp@intel.com> wrote: > > Hi Anand, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on pci/next] > [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next > patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com > patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function > config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/config) > compiler: arceb-elf-gcc (GCC) 13.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202406200818.CQ7DXNSZ-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: > >> drivers/pci/controller/pcie-rockchip.h:311:31: error: array type has incomplete element type 'struct clk_bulk_data' > 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; > | ^~~~ > I will try to fix this issue in the next version, once I get more feedback on the rest of the changes. > > vim +311 drivers/pci/controller/pcie-rockchip.h > > 298 > 299 struct rockchip_pcie { > 300 void __iomem *reg_base; /* DT axi-base */ > 301 void __iomem *apb_base; /* DT apb-base */ > 302 bool legacy_phy; > 303 struct phy *phys[MAX_LANE_NUM]; > 304 struct reset_control *core_rst; > 305 struct reset_control *mgmt_rst; > 306 struct reset_control *mgmt_sticky_rst; > 307 struct reset_control *pipe_rst; > 308 struct reset_control *pm_rst; > 309 struct reset_control *aclk_rst; > 310 struct reset_control *pclk_rst; > > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; > 312 struct regulator *vpcie12v; /* 12V power supply */ > 313 struct regulator *vpcie3v3; /* 3.3V power supply */ > 314 struct regulator *vpcie1v8; /* 1.8V power supply */ > 315 struct regulator *vpcie0v9; /* 0.9V power supply */ > 316 struct gpio_desc *ep_gpio; > 317 u32 lanes; > 318 u8 lanes_map; > 319 int link_gen; > 320 struct device *dev; > 321 struct irq_domain *irq_domain; > 322 int offset; > 323 void __iomem *msg_region; > 324 phys_addr_t msg_bus_addr; > 325 bool is_rc; > 326 struct resource *mem_res; > 327 }; > 328 > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki Thanks -Anand ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function 2024-06-18 16:41 ` [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon 2024-06-20 0:54 ` kernel test robot @ 2024-06-20 17:31 ` kernel test robot 1 sibling, 0 replies; 7+ messages in thread From: kernel test robot @ 2024-06-20 17:31 UTC (permalink / raw) To: Anand Moon, Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner Cc: llvm, oe-kbuild-all, Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Hi Anand, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240621/202406210131.rxenHeBG-lkp@intel.com/config) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240621/202406210131.rxenHeBG-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406210131.rxenHeBG-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: >> drivers/pci/controller/pcie-rockchip.h:311:28: error: array has incomplete element type 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^ drivers/pci/controller/pcie-rockchip.h:311:10: note: forward declaration of 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^ 1 error generated. vim +311 drivers/pci/controller/pcie-rockchip.h 298 299 struct rockchip_pcie { 300 void __iomem *reg_base; /* DT axi-base */ 301 void __iomem *apb_base; /* DT apb-base */ 302 bool legacy_phy; 303 struct phy *phys[MAX_LANE_NUM]; 304 struct reset_control *core_rst; 305 struct reset_control *mgmt_rst; 306 struct reset_control *mgmt_sticky_rst; 307 struct reset_control *pipe_rst; 308 struct reset_control *pm_rst; 309 struct reset_control *aclk_rst; 310 struct reset_control *pclk_rst; > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; 312 struct regulator *vpcie12v; /* 12V power supply */ 313 struct regulator *vpcie3v3; /* 3.3V power supply */ 314 struct regulator *vpcie1v8; /* 1.8V power supply */ 315 struct regulator *vpcie0v9; /* 0.9V power supply */ 316 struct gpio_desc *ep_gpio; 317 u32 lanes; 318 u8 lanes_map; 319 int link_gen; 320 struct device *dev; 321 struct irq_domain *irq_domain; 322 int offset; 323 void __iomem *msg_region; 324 phys_addr_t msg_bus_addr; 325 bool is_rc; 326 struct resource *mem_res; 327 }; 328 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function [not found] <20240618164133.223194-1-linux.amoon@gmail.com> 2024-06-18 16:41 ` [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon @ 2024-06-18 16:41 ` Anand Moon 2024-06-20 3:27 ` kernel test robot 2024-06-18 16:41 ` [PATCH v1 3/3] PCI: rockchip: refactor rockchip_pcie_disable_clocks function signature Anand Moon 2 siblings, 1 reply; 7+ messages in thread From: Anand Moon @ 2024-06-18 16:41 UTC (permalink / raw) To: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner, Philipp Zabel Cc: Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Refactors the reset control clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler. As per rockchip rk3399 TRM SOFTRST_CON8 soft reset controller have clock reset unit value set to 0x1 for example "pcie_pipe", "pcie_mgmt_sticky", "pcie_mgmt" and "pci_core", hence group then under one reset bulk controller. Where as "pcie_pm", "presetn_pcie", "aresetn_pcie" have reset value set to 0x0 ,hence group them under reset control bulk controller. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- drivers/pci/controller/pcie-rockchip.c | 139 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 24 +++-- 2 files changed, 44 insertions(+), 119 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 166dad666a35..5154dfb1311b 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -69,54 +69,24 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) if (rockchip->link_gen < 0 || rockchip->link_gen > 2) rockchip->link_gen = 2; - rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(rockchip->core_rst)) { - if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) - dev_err(dev, "missing core reset property in node\n"); - return PTR_ERR(rockchip->core_rst); - } - - rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); - if (IS_ERR(rockchip->mgmt_rst)) { - if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt reset property in node\n"); - return PTR_ERR(rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, - "mgmt-sticky"); - if (IS_ERR(rockchip->mgmt_sticky_rst)) { - if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt-sticky reset property in node\n"); - return PTR_ERR(rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(rockchip->pipe_rst)) { - if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pipe reset property in node\n"); - return PTR_ERR(rockchip->pipe_rst); - } + for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); - if (IS_ERR(rockchip->pm_rst)) { - if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pm reset property in node\n"); - return PTR_ERR(rockchip->pm_rst); + err = devm_reset_control_bulk_get_optional_exclusive(dev, + ROCKCHIP_NUM_PM_RSTS, rockchip->pm_rsts); + if (err) { + dev_err(dev, "cannot get the devm_reset_control err %d\n", err); + return err; } - rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); - if (IS_ERR(rockchip->pclk_rst)) { - if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pclk reset property in node\n"); - return PTR_ERR(rockchip->pclk_rst); - } + for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); - if (IS_ERR(rockchip->aclk_rst)) { - if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing aclk reset property in node\n"); - return PTR_ERR(rockchip->aclk_rst); + err = devm_reset_control_bulk_get_optional_exclusive(dev, + ROCKCHIP_NUM_CORE_RSTS, rockchip->core_rsts); + if (err) { + dev_err(dev, "cannot get the devm_reset_control err %d\n", err); + return err; } if (rockchip->is_rc) { @@ -152,21 +122,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) int err, i; u32 regs; - err = reset_control_assert(rockchip->aclk_rst); + err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, + rockchip->pm_rsts); if (err) { - dev_err(dev, "assert aclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pclk_rst); - if (err) { - dev_err(dev, "assert pclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pm_rst); - if (err) { - dev_err(dev, "assert pm_rst err %d\n", err); + dev_err(dev, "reset bulk assert pm_rsts err %d\n", err); return err; } @@ -178,47 +137,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err = reset_control_assert(rockchip->core_rst); + err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, + rockchip->core_rsts); if (err) { - dev_err(dev, "assert core_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "assert mgmt_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_sticky_rst); - if (err) { - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "assert pipe_rst err %d\n", err); + dev_err(dev, "reset bulk assert core_rsts err %d\n", err); goto err_exit_phy; } udelay(10); - err = reset_control_deassert(rockchip->pm_rst); - if (err) { - dev_err(dev, "deassert pm_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->aclk_rst); - if (err) { - dev_err(dev, "deassert aclk_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->pclk_rst); + err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, + rockchip->pm_rsts); if (err) { - dev_err(dev, "deassert pclk_rst err %d\n", err); + dev_err(dev, "reset bulk deassert pm_rsts err %d\n", err); goto err_exit_phy; } @@ -261,31 +192,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) * Please don't reorder the deassert sequence of the following * four reset pins. */ - err = reset_control_deassert(rockchip->mgmt_sticky_rst); + err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, + rockchip->core_rsts); if (err) { - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->core_rst); - if (err) { - dev_err(dev, "deassert core_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "deassert mgmt_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "deassert pipe_rst err %d\n", err); + dev_err(dev, "reset bulk deassert core_rsts err %d\n", err); goto err_power_off_phy; } return 0; + err_power_off_phy: while (i--) phy_power_off(rockchip->phys[i]); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index f256cdf4fa49..fceb6f526b72 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -288,6 +288,8 @@ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) #define ROCKCHIP_NUM_CLKS ARRAY_SIZE(rockchip_pci_clks) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) static const char * const rockchip_pci_clks[] = { "aclk", @@ -296,18 +298,26 @@ static const char * const rockchip_pci_clks[] = { "pm", }; +static const char * const rockchip_pci_pm_rsts[] = { + "pm", + "pclk", + "aclk", +}; + +static const char * const rockchip_pci_core_rsts[] = { + "core", + "mgmt", + "mgmt-sticky", + "pipe", +}; + struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ bool legacy_phy; struct phy *phys[MAX_LANE_NUM]; - struct reset_control *core_rst; - struct reset_control *mgmt_rst; - struct reset_control *mgmt_sticky_rst; - struct reset_control *pipe_rst; - struct reset_control *pm_rst; - struct reset_control *aclk_rst; - struct reset_control *pclk_rst; + struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS]; + struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS]; struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; struct regulator *vpcie12v; /* 12V power supply */ struct regulator *vpcie3v3; /* 3.3V power supply */ -- 2.44.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function 2024-06-18 16:41 ` [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Anand Moon @ 2024-06-20 3:27 ` kernel test robot 0 siblings, 0 replies; 7+ messages in thread From: kernel test robot @ 2024-06-20 3:27 UTC (permalink / raw) To: Anand Moon, Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner, Philipp Zabel Cc: oe-kbuild-all, Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Hi Anand, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240618164133.223194-3-linux.amoon%40gmail.com patch subject: [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406201156.PPCyjK8r-lkp@intel.com/config) compiler: arceb-elf-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406201156.PPCyjK8r-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406201156.PPCyjK8r-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: >> drivers/pci/controller/pcie-rockchip.h:319:41: error: array type has incomplete element type 'struct reset_control_bulk_data' 319 | struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS]; | ^~~~~~~ drivers/pci/controller/pcie-rockchip.h:320:41: error: array type has incomplete element type 'struct reset_control_bulk_data' 320 | struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS]; | ^~~~~~~~~ drivers/pci/controller/pcie-rockchip.h:321:31: error: array type has incomplete element type 'struct clk_bulk_data' 321 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^~~~ vim +319 drivers/pci/controller/pcie-rockchip.h 313 314 struct rockchip_pcie { 315 void __iomem *reg_base; /* DT axi-base */ 316 void __iomem *apb_base; /* DT apb-base */ 317 bool legacy_phy; 318 struct phy *phys[MAX_LANE_NUM]; > 319 struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS]; 320 struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS]; 321 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; 322 struct regulator *vpcie12v; /* 12V power supply */ 323 struct regulator *vpcie3v3; /* 3.3V power supply */ 324 struct regulator *vpcie1v8; /* 1.8V power supply */ 325 struct regulator *vpcie0v9; /* 0.9V power supply */ 326 struct gpio_desc *ep_gpio; 327 u32 lanes; 328 u8 lanes_map; 329 int link_gen; 330 struct device *dev; 331 struct irq_domain *irq_domain; 332 int offset; 333 void __iomem *msg_region; 334 phys_addr_t msg_bus_addr; 335 bool is_rc; 336 struct resource *mem_res; 337 }; 338 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 3/3] PCI: rockchip: refactor rockchip_pcie_disable_clocks function signature [not found] <20240618164133.223194-1-linux.amoon@gmail.com> 2024-06-18 16:41 ` [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon 2024-06-18 16:41 ` [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Anand Moon @ 2024-06-18 16:41 ` Anand Moon 2 siblings, 0 replies; 7+ messages in thread From: Anand Moon @ 2024-06-18 16:41 UTC (permalink / raw) To: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Heiko Stuebner Cc: Anand Moon, linux-pci, linux-rockchip, linux-arm-kernel, linux-kernel Updated rockchip_pcie_disable_clocks function to accept a struct rockchip pointer instead of a void pointer. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- drivers/pci/controller/pcie-rockchip.c | 4 +--- drivers/pci/controller/pcie-rockchip.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 5154dfb1311b..79f625cba11c 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -282,10 +282,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) } EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); -void rockchip_pcie_disable_clocks(void *data) +void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip) { - struct rockchip_pcie *rockchip = data; - clk_bulk_disable_unprepare(ROCKCHIP_NUM_CLKS, rockchip->clks); } EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index fceb6f526b72..6fe5c32af0ee 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -352,7 +352,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip); int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); -void rockchip_pcie_disable_clocks(void *data); +void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip); void rockchip_pcie_cfg_configuration_accesses( struct rockchip_pcie *rockchip, u32 type); -- 2.44.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-06-20 17:32 UTC | newest]
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[not found] <20240618164133.223194-1-linux.amoon@gmail.com>
2024-06-18 16:41 ` [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon
2024-06-20 0:54 ` kernel test robot
2024-06-20 2:15 ` Anand Moon
2024-06-20 17:31 ` kernel test robot
2024-06-18 16:41 ` [PATCH v1 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Anand Moon
2024-06-20 3:27 ` kernel test robot
2024-06-18 16:41 ` [PATCH v1 3/3] PCI: rockchip: refactor rockchip_pcie_disable_clocks function signature Anand Moon
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