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Thu, 20 Jun 2024 23:37:12 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45KNbAx3016285 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Jun 2024 23:37:11 GMT Received: from hu-eberman-lv.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Jun 2024 16:37:10 -0700 Date: Thu, 20 Jun 2024 16:37:09 -0700 From: Elliot Berman To: Sudeep Holla , Sebastian Reichel CC: Bjorn Andersson , Konrad Dybcio , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Andy Yan , Lorenzo Pieralisi , "Mark Rutland" , Bartosz Golaszewski , Satya Durga Srinivasu Prabhala , Melody Olvera , Shivendra Pratap , , , , Florian Fainelli , , Subject: Re: [PATCH v5 3/4] firmware: psci: Read and use vendor reset types Message-ID: <20240620162547309-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20240617-arm-psci-system_reset2-vendor-reboots-v5-0-086950f650c8@quicinc.com> <20240617-arm-psci-system_reset2-vendor-reboots-v5-3-086950f650c8@quicinc.com> <20240619135143.kr2tx4ynxayc5v3a@bogus> <20240619080933071-0700.eberman@hu-eberman-lv.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240619080933071-0700.eberman@hu-eberman-lv.qualcomm.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FPdfh-nyfdNH2V3YNMdyeKVIT0F722rp X-Proofpoint-ORIG-GUID: FPdfh-nyfdNH2V3YNMdyeKVIT0F722rp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-20_10,2024-06-20_04,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406200172 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_163720_180862_1B91E3C3 X-CRM114-Status: GOOD ( 39.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sudeep and Sebastian, On Wed, Jun 19, 2024 at 08:28:06AM -0700, Elliot Berman wrote: > On Wed, Jun 19, 2024 at 02:51:43PM +0100, Sudeep Holla wrote: > > On Mon, Jun 17, 2024 at 10:18:09AM -0700, Elliot Berman wrote: > > > SoC vendors have different types of resets and are controlled through > > > various registers. For instance, Qualcomm chipsets can reboot to a > > > "download mode" that allows a RAM dump to be collected. Another example > > > is they also support writing a cookie that can be read by bootloader > > > during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these > > > vendor reset types to be implemented without requiring drivers for every > > > register/cookie. > > > > > > Add support in PSCI to statically map reboot mode commands from > > > userspace to a vendor reset and cookie value using the device tree. > > > > > > A separate initcall is needed to parse the devicetree, instead of using > > > psci_dt_init because mm isn't sufficiently set up to allocate memory. > > > > > > Reboot mode framework is close but doesn't quite fit with the > > > design and requirements for PSCI SYSTEM_RESET2. Some of these issues can > > > be solved but doesn't seem reasonable in sum: > > > 1. reboot mode registers against the reboot_notifier_list, which is too > > > early to call SYSTEM_RESET2. PSCI would need to remember the reset > > > type from the reboot-mode framework callback and use it > > > psci_sys_reset. > > > 2. reboot mode assumes only one cookie/parameter is described in the > > > device tree. SYSTEM_RESET2 uses 2: one for the type and one for > > > cookie. > > > 3. psci cpuidle driver already registers a driver against the > > > arm,psci-1.0 compatible. Refactoring would be needed to have both a > > > cpuidle and reboot-mode driver. > > > > > > > I need to think through it but when you first introduced the generic > > Documentation/devicetree/bindings/power/reset/reboot-mode.yaml bindings > > I also looked at drivers/power/reset/reboot-mode.c > > > > I assumed this extension to that binding would reuse the same and > > PSCI would just do reboot_mode_register(). I didn't expect to see these > > changes. I might have missing something but since the bindings is still > > quite generic with additional cells that act as additional cookie for > > reboot call, I still think that should be possible. > > > > What am I missing here then ? > > > > Right, if that was only thing to "solve" to make it easy to use > reboot-mode framework, I agree we should update reboot mode framework to > work with the additional cells. There are a few other issues I mention > above which, when combined, make me feel that PSCI is different enough > from how reboot mode framework works that we shouldn't try to make PSCI > work with the framework. Issues #1 and #2 are pretty easy to solve > (whether they should be solved is different); I'm not sure a good > approach to issue #3. > Does the reasoning I mention in the commit text make sense why PSCI should avoid using the reboot-mode.c framework? Thanks, Elliot