[boot-wrapper 0/7] Add Armv8-R AArch64 support

[boot-wrapper 0/7] Add Armv8-R AArch64 support

[Luca Fancellu]

Currently, we cannot boot Linux with boot-wrapper on Armv8-R AArch64:
1. The Armv8-R AArch64 profile does not support the EL3.
2. The Armv8-R AArch64 EL2 only supports a PMSA, which Linux does not
support. So it's necessary to drop into EL1 before entering the kernel.
3. There is no EL2 booting code for Armv8-R AArch64 and no
configuration for dropping to EL1 in boot-wrapper.

These patches enable boot-wrapper booting Linux with Armv8-R AArch64.

This is a rework and rebase of a serie already present upstream [1], apart
from patch 3 which is addressing a small bug and patch 6 and 7 which are
introducing support for PSCI boot through hvc conduit and Xen boot under Armv8-R
AArch64.

[1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210525062509.201464-1-jaxson.han@arm.com/

Luca Fancellu (7):
  aarch64: Rename labels and prepare for lower EL booting
  aarch64: Prepare for lower EL booting
  aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET
  gic-v3: Prepare for gicv3 with EL2
  aarch64: Introduce EL2 boot code for Armv8-R AArch64
  aarch64: Support PSCI for Armv8-R AArch64
  aarch64: Start Xen on Armv8-R at EL2

 Makefile.am                       |  6 ++-
 arch/aarch32/include/asm/gic-v3.h |  7 +++
 arch/aarch64/boot.S               | 86 ++++++++++++++++++++++++++++---
 arch/aarch64/include/asm/cpu.h    | 14 ++++-
 arch/aarch64/include/asm/gic-v3.h | 20 +++++--
 arch/aarch64/init.c               | 39 ++++++++++++--
 common/gic-v3.c                   |  2 +-
 configure.ac                      | 19 +++++--
 8 files changed, 170 insertions(+), 23 deletions(-)

-- 
2.34.1


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[boot-wrapper 1/7] aarch64: Rename labels and prepare for lower EL booting

[Luca Fancellu]

The current code can boot from a lower EL than EL3, but the flag
'flag_no_el3' have the meaning of "Don't drop to a lower EL", so
rename the flag to flag_keep_el.
This is a preparation work to boot on Armv8-R AArch64 which has
no EL3.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch64/boot.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index da5fa6548b65..7727475925c1 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -92,7 +92,7 @@ reset_no_el3:
 	bl	setup_stack
 
 	mov	w0, #1
-	ldr	x1, =flag_no_el3
+	ldr	x1, =flag_keep_el
 	str	w0, [x1]
 
 	bl	cpu_init_bootwrapper
@@ -124,7 +124,7 @@ ASM_FUNC(jump_kernel)
 	bl	find_logical_id
 	bl	setup_stack		// Reset stack pointer
 
-	ldr	w0, flag_no_el3
+	ldr	w0, flag_keep_el
 	cmp	w0, #0			// Prepare Z flag
 
 	mov	x0, x20
@@ -133,7 +133,7 @@ ASM_FUNC(jump_kernel)
 	mov	x3, x23
 
 	b.eq	1f
-	br	x19			// No EL3
+	br	x19			// Keep EL
 
 1:	mov	x4, #SPSR_KERNEL
 
@@ -151,5 +151,5 @@ ASM_FUNC(jump_kernel)
 
 	.data
 	.align 3
-flag_no_el3:
+flag_keep_el:
 	.long 0
-- 
2.34.1


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[boot-wrapper 2/7] aarch64: Prepare for lower EL booting

[Luca Fancellu]

Store the value of the initial SPSR into a variable during
EL3 initialization and load it from the variable before dropping
EL, this is done as preparation work to be able to boot from a
different exception level.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch64/boot.S | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 7727475925c1..211077af17c8 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -51,6 +51,10 @@ reset_at_el3:
 	b.eq	err_invalid_id
 	bl	setup_stack
 
+	mov	w0, #SPSR_KERNEL
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+
 	bl	cpu_init_bootwrapper
 
 	bl	cpu_init_el3
@@ -135,7 +139,7 @@ ASM_FUNC(jump_kernel)
 	b.eq	1f
 	br	x19			// Keep EL
 
-1:	mov	x4, #SPSR_KERNEL
+1:	ldr	w4, spsr_to_elx
 
 	/*
 	 * If bit 0 of the kernel address is set, we're entering in AArch32
@@ -153,3 +157,5 @@ ASM_FUNC(jump_kernel)
 	.align 3
 flag_keep_el:
 	.long 0
+spsr_to_elx:
+	.long 0
-- 
2.34.1


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[boot-wrapper 3/7] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET

[Luca Fancellu]

From the specification SCTLR_EL2.TSCXT is RES1 only "When
FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not
implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so
given that HCR_EL2.E2H is set by bootwrapper before to a
value of zero, the condition above can't happen and from
the specification the bit is RES0.

Fix the macro removing the bit.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 124ef916ddfc..846b89f8405d 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -30,8 +30,8 @@
 	 BIT(11) | BIT(5) | BIT(4))
 
 #define SCTLR_EL2_RES1							\
-	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) |	\
-	 BIT(16) | BIT(11) | BIT(5) | BIT(4))
+	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) |	\
+	 BIT(11) | BIT(5) | BIT(4))
 
 #define SCTLR_EL1_RES1							\
 	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) |	\
-- 
2.34.1


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[boot-wrapper 4/7] gic-v3: Prepare for gicv3 with EL2

[Luca Fancellu]

This is a preparation for allowing boot-wrapper configuring the gicv3
with EL2.

When supporting boot at EL2 for Armv8-R, the architecture does not
define ICC_CTLR_EL2.
See [https://developer.arm.com/documentation/ihi0069/latest/].

As the caller, gic_secure_init expects the ICC_CTLR to be written,
we change the function into gic_init_icc_ctlr(). In the GIC spec,
the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
(not applicable since no EL3), non-secure IRQ handling (not applicable
since only secure state in Armv8-R aarch64), or are aliased to
ICC_CTLR_EL1 bits.
So, based on this, the new gic_init_icc_ctlr() would be:
When currentEL is EL3, init ICC_CTLR_EL3 as before.
When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch32/include/asm/gic-v3.h |  7 +++++++
 arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++---
 common/gic-v3.c                   |  2 +-
 3 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
index b28136af7fe1..fdfbef859517 100644
--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
@@ -11,6 +11,8 @@
 
 #include <asm/cpu.h>
 
+#define ICC_CTLR_RESET (0UL)
+
 static inline void gic_write_icc_sre(uint32_t val)
 {
 	mcr(ICC_SRE, val);
@@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
 	mcr(ICC_CTLR, val);
 }
 
+static inline void gic_init_icc_ctlr()
+{
+	gic_write_icc_ctlr(ICC_CTLR_RESET);
+}
+
 #endif
diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
index 24474807c6fe..aca7ab140ed5 100644
--- a/arch/aarch64/include/asm/gic-v3.h
+++ b/arch/aarch64/include/asm/gic-v3.h
@@ -11,14 +11,28 @@
 
 #include <asm/cpu.h>
 
+#define ICC_CTLR_EL3_RESET     (0UL)
+#define ICC_CTLR_EL1_RESET     (0UL)
+
+static inline uint32_t current_el(void)
+{
+	return mrs(CurrentEL);
+}
+
 static inline void gic_write_icc_sre(uint32_t val)
 {
-	msr(ICC_SRE_EL3, val);
+	if (current_el() == CURRENTEL_EL3)
+		msr(ICC_SRE_EL3, val);
+	else
+		msr(ICC_SRE_EL2, val);
 }
 
-static inline void gic_write_icc_ctlr(uint32_t val)
+static inline void gic_init_icc_ctlr()
 {
-	msr(ICC_CTLR_EL3, val);
+	if (current_el() == CURRENTEL_EL3)
+		msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET);
+	else
+		msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET);
 }
 
 #endif
diff --git a/common/gic-v3.c b/common/gic-v3.c
index 6207007959bd..a0fe5642257e 100644
--- a/common/gic-v3.c
+++ b/common/gic-v3.c
@@ -117,6 +117,6 @@ void gic_secure_init(void)
 	gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE);
 	isb();
 
-	gic_write_icc_ctlr(0);
+	gic_init_icc_ctlr();
 	isb();
 }
-- 
2.34.1


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[boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Luca Fancellu]

The Armv8-R AArch64 profile does not support the EL3 exception level.
The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
at EL1, which allows to run off-the-shelf Linux. However EL2 only
supports a PMSA, which is not supported by Linux, so we need to drop
into EL1 before entering the kernel.

We add a new err_invalid_arch symbol as a dead loop. If we detect the
current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot
Linux anymore, then we jump to err_invalid_arch.

During Armv8-R aarch64 init, to make sure nothing unexpected traps into
EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2.

The boot sequence is:
If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
  before entering the kernel.
If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
  if id_aa64mmfr0_el1.MSA_frac == 0x2,
    then goto Armv8-R AArch64 initialisation and drop to EL1 before
    entering the kernel.
  else, which means VMSA unsupported and cannot boot Linux,
    goto err_invalid_arch (dead loop).
Else, no initialisation and keep the current EL before entering the
  kernel.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch64/boot.S            | 63 ++++++++++++++++++++++++++++++++--
 arch/aarch64/include/asm/cpu.h | 10 ++++++
 arch/aarch64/init.c            | 24 +++++++++++++
 3 files changed, 94 insertions(+), 3 deletions(-)

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 211077af17c8..b2b9863b8d6a 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -22,7 +22,8 @@
 	 *   EL2 must be implemented.
 	 *
 	 * - EL2 (Non-secure)
-	 *   Entering at EL2 is partially supported.
+	 *   Entering at EL2 is partially supported for Armv8-A.
+	 *   Entering at EL2 is supported for Armv8-R.
 	 *   PSCI is not supported when entered in this exception level.
 	 */
 ASM_FUNC(_start)
@@ -76,7 +77,50 @@ reset_at_el2:
 	msr	sctlr_el2, x0
 	isb
 
-	b	reset_no_el3
+	/* Detect Armv8-R AArch64 */
+	mrs	x1, id_aa64mmfr0_el1
+	/*
+	 * Check MSA, bits [51:48]:
+	 * 0xf means Armv8-R AArch64.
+	 * If not 0xf, proceed in Armv8-A EL2.
+	 */
+	ubfx	x0, x1, #48, #4			// MSA
+	cmp	x0, 0xf
+	bne	reset_no_el3
+
+	/*
+	 * Armv8-R AArch64 is found, check if Linux can be booted.
+	 * Check MSA_frac, bits [55:52]:
+	 * 0x2 means EL1&0 translation regime also supports VMSAv8-64.
+	 */
+	ubfx	x0, x1, #52, #4			// MSA_frac
+	cmp	x0, 0x2
+	/*
+	 * If not 0x2, no VMSA, so cannot boot Linux and dead loop.
+	 * Also, since the architecture guarantees that those CPUID
+	 * fields never lose features when the value in a field
+	 * increases, we use blt to cover it.
+	 */
+	blt	err_invalid_arch
+
+	/* Start Armv8-R Linux at EL1 */
+	mov	w0, #SPSR_KERNEL_EL1
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+
+	cpuid	x0, x1
+	bl	find_logical_id
+	cmp	x0, #MPIDR_INVALID
+	b.eq	err_invalid_id
+	bl	setup_stack
+
+	bl	cpu_init_bootwrapper
+
+	bl	cpu_init_armv8r_el2
+
+	bl	gic_secure_init
+
+	b	start_bootmethod
 
 	/*
 	 * EL1 initialization
@@ -104,6 +148,7 @@ reset_no_el3:
 	b	start_bootmethod
 
 err_invalid_id:
+err_invalid_arch:
 	b	.
 
 	/*
@@ -121,10 +166,14 @@ ASM_FUNC(jump_kernel)
 	ldr	x0, =SCTLR_EL1_KERNEL
 	msr	sctlr_el1, x0
 
+	mrs	x5, CurrentEL
+	cmp	x5, #CURRENTEL_EL2
+	b.eq	1f
+
 	ldr	x0, =SCTLR_EL2_KERNEL
 	msr	sctlr_el2, x0
 
-	cpuid	x0, x1
+1:	cpuid	x0, x1
 	bl	find_logical_id
 	bl	setup_stack		// Reset stack pointer
 
@@ -147,10 +196,18 @@ ASM_FUNC(jump_kernel)
 	 */
 	bfi	x4, x19, #5, #1
 
+	mrs	x5, CurrentEL
+	cmp	x5, #CURRENTEL_EL2
+	b.eq	1f
+
 	msr	elr_el3, x19
 	msr	spsr_el3, x4
 	eret
 
+1:	msr	elr_el2, x19
+	msr	spsr_el2, x4
+	eret
+
 	.ltorg
 
 	.data
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 846b89f8405d..6b2f5fbe4502 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -58,7 +58,13 @@
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_PIEN			BIT(45)
 
+#define VTCR_EL2_MSA			BIT(31)
+
 #define HCR_EL2_RES1			BIT(1)
+#define HCR_EL2_APK_NOTRAP		BIT(40)
+#define HCR_EL2_API_NOTRAP		BIT(41)
+#define HCR_EL2_FIEN_NOTRAP		BIT(47)
+#define HCR_EL2_ENSCXT_NOTRAP	BIT(53)
 
 #define ID_AA64DFR0_EL1_PMSVER		BITS(35, 32)
 #define ID_AA64DFR0_EL1_TRACEBUFFER	BITS(47, 44)
@@ -88,7 +94,9 @@
 
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
+#define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
 #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
+#define ID_AA64PFR0_EL1_CSV2	BITS(59, 56)
 
 #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
 #define ID_AA64SMFR0_EL1_FA64		BIT(63)
@@ -114,6 +122,7 @@
 #define SPSR_I			(1 << 7)	/* IRQ masked */
 #define SPSR_F			(1 << 6)	/* FIQ masked */
 #define SPSR_T			(1 << 5)	/* Thumb */
+#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
 #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
 #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
 
@@ -153,6 +162,7 @@
 #else
 #define SCTLR_EL1_KERNEL	SCTLR_EL1_RES1
 #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
+#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
 #endif
 
 #ifndef __ASSEMBLY__
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 37cb45fde446..8006f2705193 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -145,6 +145,30 @@ void cpu_init_el3(void)
 	msr(CNTFRQ_EL0, COUNTER_FREQ);
 }
 
+void cpu_init_armv8r_el2(void)
+{
+	unsigned long hcr = mrs(hcr_el2);
+
+	msr(vpidr_el2, mrs(midr_el1));
+	msr(vmpidr_el2, mrs(mpidr_el1));
+
+	/* VTCR_MSA: VMSAv8-64 support */
+	msr(vtcr_el2, VTCR_EL2_MSA);
+
+	if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2)
+		hcr |= HCR_EL2_ENSCXT_NOTRAP;
+
+	if (mrs_field(ID_AA64PFR0_EL1, RAS) <= 2)
+		hcr |= HCR_EL2_FIEN_NOTRAP;
+
+	if (cpu_has_pauth())
+		hcr |= HCR_EL2_APK_NOTRAP | HCR_EL2_API_NOTRAP;
+
+	msr(hcr_el2, hcr);
+	isb();
+	msr(CNTFRQ_EL0, COUNTER_FREQ);
+}
+
 #ifdef PSCI
 extern char psci_vectors[];
 
-- 
2.34.1


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[boot-wrapper 6/7] aarch64: Support PSCI for Armv8-R AArch64

[Luca Fancellu]

Add support for PSCI when booting Linux on Armv8-R AArch64,
allow the autoconf parameter --enable-psci to take an argument
which is the conduit to be used, it can be empty or 'smc' to
select the smc conduit, it can be 'hvc' for the hvc conduit.

Depending on the selected conduit, the vector table will be
installed on the VBAR_EL3 or VBAR_EL2 register.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 Makefile.am         |  5 ++++-
 arch/aarch64/init.c | 15 ++++++++++++---
 configure.ac        | 16 +++++++++++-----
 3 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/Makefile.am b/Makefile.am
index 6ebece25b230..34fbfb1f4ff8 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -49,11 +49,14 @@ endif
 
 if PSCI
 DEFINES		+= -DPSCI
+if PSCI_HVC
+DEFINES		+= -DPSCI_HVC
+endif
 ARCH_OBJ	+= psci.o
 COMMON_OBJ	+= psci.o
 PSCI_NODE	:= psci {				\
 			compatible = \"arm,psci\";	\
-			method = \"smc\";		\
+			method = \"$(PSCI_METHOD)\";	\
 			cpu_on = <$(PSCI_CPU_ON)>;	\
 			cpu_off = <$(PSCI_CPU_OFF)>;	\
 		   };
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 8006f2705193..3305e69270a4 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -174,10 +174,19 @@ extern char psci_vectors[];
 
 bool cpu_init_psci_arch(void)
 {
-	if (mrs(CurrentEL) != CURRENTEL_EL3)
+	switch (mrs(CurrentEL)) {
+#if !defined(PSCI_HVC)
+	case CURRENTEL_EL3:
+		msr(VBAR_EL3, (unsigned long)psci_vectors);
+		break;
+#else
+	case CURRENTEL_EL2:
+		msr(VBAR_EL2, (unsigned long)psci_vectors);
+		break;
+#endif
+	default:
 		return false;
-
-	msr(VBAR_EL3, (unsigned long)psci_vectors);
+	}
 	isb();
 
 	return true;
diff --git a/configure.ac b/configure.ac
index 9e3b7226cd69..44459a4c849e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -83,13 +83,19 @@ AS_IF([test "x$X_IMAGE" != "x"],
 # Allow a user to pass --enable-psci
 AC_ARG_ENABLE([psci],
 	AS_HELP_STRING([--disable-psci], [disable the psci boot method]),
-	[USE_PSCI=$enableval], [USE_PSCI="yes"])
-AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"])
-AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no])
-
-AS_IF([test "x$USE_PSCI" != "xyes" -a "x$KERNEL_ES" = "x32"],
+	[case "${enableval}" in
+		yes|smc) USE_PSCI=smc ;;
+		hvc) USE_PSCI=hvc ;;
+		no) ;;
+		*) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;;
+	esac])
+AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"])
+AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
+
+AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
 	[AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
 )
+AC_SUBST([PSCI_METHOD], [$USE_PSCI])
 
 # Allow a user to pass --with-initrd
 AC_ARG_WITH([initrd],
-- 
2.34.1


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[boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2

[Luca Fancellu]

When bootwrapper is compiled with Xen support and it is started
at EL2 on Armv8-R AArch64, keep the current EL and jump to the
Xen image.

Additionally, don't permit the usage of hvc conduit when Xen
kernel is passed, because it's not supported.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
 Makefile.am         | 1 +
 arch/aarch64/boot.S | 7 +++++++
 configure.ac        | 3 +++
 3 files changed, 11 insertions(+)

diff --git a/Makefile.am b/Makefile.am
index 34fbfb1f4ff8..bafce34682c3 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -112,6 +112,7 @@ XEN_CHOSEN	:= xen,xen-bootargs = \"$(XEN_CMDLINE)\";		\
 			compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \
 			reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>;	\
 		   };
+DEFINES		+= -DXEN
 endif
 
 if INITRD
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index b2b9863b8d6a..0b30b82ad6d9 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -88,6 +88,7 @@ reset_at_el2:
 	cmp	x0, 0xf
 	bne	reset_no_el3
 
+#if !defined(XEN)
 	/*
 	 * Armv8-R AArch64 is found, check if Linux can be booted.
 	 * Check MSA_frac, bits [55:52]:
@@ -107,6 +108,12 @@ reset_at_el2:
 	mov	w0, #SPSR_KERNEL_EL1
 	ldr	x1, =spsr_to_elx
 	str	w0, [x1]
+#else
+	/* Start XEN on Armv8-R at EL2 */
+	mov	w0, #1
+	ldr	x1, =flag_keep_el
+	str	w0, [x1]
+#endif
 
 	cpuid	x0, x1
 	bl	find_logical_id
diff --git a/configure.ac b/configure.ac
index 44459a4c849e..a5175db4148a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
 AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
 	[AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
 )
+AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"],
+	[AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])]
+)
 AC_SUBST([PSCI_METHOD], [$USE_PSCI])
 
 # Allow a user to pass --with-initrd
-- 
2.34.1


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Re: [boot-wrapper 0/7] Add Armv8-R AArch64 support

[Luca Fancellu]

Hi Mark,

This serie should have been sent to you, but I did a mess sending it only to the mailing list,
this is a convenient link to the changes:

https://lore.kernel.org/linux-arm-kernel/20240606133628.3330423-1-luca.fancellu@arm.com/T/#t

> On 6 Jun 2024, at 14:36, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
> 
> Currently, we cannot boot Linux with boot-wrapper on Armv8-R AArch64:
> 1. The Armv8-R AArch64 profile does not support the EL3.
> 2. The Armv8-R AArch64 EL2 only supports a PMSA, which Linux does not
> support. So it's necessary to drop into EL1 before entering the kernel.
> 3. There is no EL2 booting code for Armv8-R AArch64 and no
> configuration for dropping to EL1 in boot-wrapper.
> 
> These patches enable boot-wrapper booting Linux with Armv8-R AArch64.
> 
> This is a rework and rebase of a serie already present upstream [1], apart
> from patch 3 which is addressing a small bug and patch 6 and 7 which are
> introducing support for PSCI boot through hvc conduit and Xen boot under Armv8-R
> AArch64.
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210525062509.201464-1-jaxson.han@arm.com/
> 
> Luca Fancellu (7):
>  aarch64: Rename labels and prepare for lower EL booting
>  aarch64: Prepare for lower EL booting
>  aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET
>  gic-v3: Prepare for gicv3 with EL2
>  aarch64: Introduce EL2 boot code for Armv8-R AArch64
>  aarch64: Support PSCI for Armv8-R AArch64
>  aarch64: Start Xen on Armv8-R at EL2
> 
> Makefile.am                       |  6 ++-
> arch/aarch32/include/asm/gic-v3.h |  7 +++
> arch/aarch64/boot.S               | 86 ++++++++++++++++++++++++++++---
> arch/aarch64/include/asm/cpu.h    | 14 ++++-
> arch/aarch64/include/asm/gic-v3.h | 20 +++++--
> arch/aarch64/init.c               | 39 ++++++++++++--
> common/gic-v3.c                   |  2 +-
> configure.ac                      | 19 +++++--
> 8 files changed, 170 insertions(+), 23 deletions(-)

Cheers,
Luca


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Re: [boot-wrapper 1/7] aarch64: Rename labels and prepare for lower EL booting

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:22 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

> The current code can boot from a lower EL than EL3, but the flag
> 'flag_no_el3' have the meaning of "Don't drop to a lower EL", so
> rename the flag to flag_keep_el.
> This is a preparation work to boot on Armv8-R AArch64 which has
> no EL3.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  arch/aarch64/boot.S | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index da5fa6548b65..7727475925c1 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -92,7 +92,7 @@ reset_no_el3:
>  	bl	setup_stack
>  
>  	mov	w0, #1
> -	ldr	x1, =flag_no_el3
> +	ldr	x1, =flag_keep_el
>  	str	w0, [x1]
>  
>  	bl	cpu_init_bootwrapper
> @@ -124,7 +124,7 @@ ASM_FUNC(jump_kernel)
>  	bl	find_logical_id
>  	bl	setup_stack		// Reset stack pointer
>  
> -	ldr	w0, flag_no_el3
> +	ldr	w0, flag_keep_el
>  	cmp	w0, #0			// Prepare Z flag
>  
>  	mov	x0, x20
> @@ -133,7 +133,7 @@ ASM_FUNC(jump_kernel)
>  	mov	x3, x23
>  
>  	b.eq	1f
> -	br	x19			// No EL3
> +	br	x19			// Keep EL
>  
>  1:	mov	x4, #SPSR_KERNEL
>  
> @@ -151,5 +151,5 @@ ASM_FUNC(jump_kernel)
>  
>  	.data
>  	.align 3
> -flag_no_el3:
> +flag_keep_el:
>  	.long 0


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Re: [boot-wrapper 2/7] aarch64: Prepare for lower EL booting

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:23 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

Hi,

> Store the value of the initial SPSR into a variable during
> EL3 initialization and load it from the variable before dropping
> EL, this is done as preparation work to be able to boot from a
> different exception level.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  arch/aarch64/boot.S | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 7727475925c1..211077af17c8 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -51,6 +51,10 @@ reset_at_el3:
>  	b.eq	err_invalid_id
>  	bl	setup_stack
>  
> +	mov	w0, #SPSR_KERNEL
> +	ldr	x1, =spsr_to_elx
> +	str	w0, [x1]
> +
>  	bl	cpu_init_bootwrapper
>  
>  	bl	cpu_init_el3
> @@ -135,7 +139,7 @@ ASM_FUNC(jump_kernel)
>  	b.eq	1f
>  	br	x19			// Keep EL
>  
> -1:	mov	x4, #SPSR_KERNEL
> +1:	ldr	w4, spsr_to_elx
>  
>  	/*
>  	 * If bit 0 of the kernel address is set, we're entering in AArch32
> @@ -153,3 +157,5 @@ ASM_FUNC(jump_kernel)
>  	.align 3
>  flag_keep_el:
>  	.long 0
> +spsr_to_elx:
> +	.long 0


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Re: [boot-wrapper 3/7] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:24 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

> From the specification SCTLR_EL2.TSCXT is RES1 only "When
> FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not
> implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so
> given that HCR_EL2.E2H is set by bootwrapper before to a
> value of zero, the condition above can't happen and from
> the specification the bit is RES0.
> 
> Fix the macro removing the bit.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks,
Andre

> ---
>  arch/aarch64/include/asm/cpu.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 124ef916ddfc..846b89f8405d 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -30,8 +30,8 @@
>  	 BIT(11) | BIT(5) | BIT(4))
>  
>  #define SCTLR_EL2_RES1							\
> -	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) |	\
> -	 BIT(16) | BIT(11) | BIT(5) | BIT(4))
> +	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) |	\
> +	 BIT(11) | BIT(5) | BIT(4))
>  
>  #define SCTLR_EL1_RES1							\
>  	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) |	\


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Re: [boot-wrapper 4/7] gic-v3: Prepare for gicv3 with EL2

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:25 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

Hi,

> This is a preparation for allowing boot-wrapper configuring the gicv3
> with EL2.
> 
> When supporting boot at EL2 for Armv8-R, the architecture does not
> define ICC_CTLR_EL2.
> See [https://developer.arm.com/documentation/ihi0069/latest/].
> 
> As the caller, gic_secure_init expects the ICC_CTLR to be written,
> we change the function into gic_init_icc_ctlr(). In the GIC spec,
> the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
> (not applicable since no EL3), non-secure IRQ handling (not applicable
> since only secure state in Armv8-R aarch64), or are aliased to
> ICC_CTLR_EL1 bits.
> So, based on this, the new gic_init_icc_ctlr() would be:
> When currentEL is EL3, init ICC_CTLR_EL3 as before.
> When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.

Looks alright, for the purpose of initialising the registers with zero,
the two registers behave the same.

> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  arch/aarch32/include/asm/gic-v3.h |  7 +++++++
>  arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++---
>  common/gic-v3.c                   |  2 +-
>  3 files changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
> index b28136af7fe1..fdfbef859517 100644
> --- a/arch/aarch32/include/asm/gic-v3.h
> +++ b/arch/aarch32/include/asm/gic-v3.h
> @@ -11,6 +11,8 @@
>  
>  #include <asm/cpu.h>
>  
> +#define ICC_CTLR_RESET (0UL)
> +
>  static inline void gic_write_icc_sre(uint32_t val)
>  {
>  	mcr(ICC_SRE, val);
> @@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
>  	mcr(ICC_CTLR, val);
>  }
>  
> +static inline void gic_init_icc_ctlr()
> +{
> +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> +}
> +
>  #endif
> diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
> index 24474807c6fe..aca7ab140ed5 100644
> --- a/arch/aarch64/include/asm/gic-v3.h
> +++ b/arch/aarch64/include/asm/gic-v3.h
> @@ -11,14 +11,28 @@
>  
>  #include <asm/cpu.h>
>  
> +#define ICC_CTLR_EL3_RESET     (0UL)
> +#define ICC_CTLR_EL1_RESET     (0UL)
> +
> +static inline uint32_t current_el(void)
> +{
> +	return mrs(CurrentEL);
> +}
> +
>  static inline void gic_write_icc_sre(uint32_t val)
>  {
> -	msr(ICC_SRE_EL3, val);
> +	if (current_el() == CURRENTEL_EL3)
> +		msr(ICC_SRE_EL3, val);
> +	else
> +		msr(ICC_SRE_EL2, val);
>  }
>  
> -static inline void gic_write_icc_ctlr(uint32_t val)
> +static inline void gic_init_icc_ctlr()
>  {
> -	msr(ICC_CTLR_EL3, val);
> +	if (current_el() == CURRENTEL_EL3)
> +		msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET);
> +	else
> +		msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET);
>  }
>  
>  #endif
> diff --git a/common/gic-v3.c b/common/gic-v3.c
> index 6207007959bd..a0fe5642257e 100644
> --- a/common/gic-v3.c
> +++ b/common/gic-v3.c
> @@ -117,6 +117,6 @@ void gic_secure_init(void)
>  	gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE);
>  	isb();
>  
> -	gic_write_icc_ctlr(0);
> +	gic_init_icc_ctlr();
>  	isb();
>  }


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Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:26 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

Hi,

> The Armv8-R AArch64 profile does not support the EL3 exception level.
> The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
> at EL1, which allows to run off-the-shelf Linux. However EL2 only
> supports a PMSA, which is not supported by Linux, so we need to drop
> into EL1 before entering the kernel.
> 
> We add a new err_invalid_arch symbol as a dead loop. If we detect the
> current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot
> Linux anymore, then we jump to err_invalid_arch.
> 
> During Armv8-R aarch64 init, to make sure nothing unexpected traps into
> EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2.
> 
> The boot sequence is:
> If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
>   before entering the kernel.
> If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
>   if id_aa64mmfr0_el1.MSA_frac == 0x2,
>     then goto Armv8-R AArch64 initialisation and drop to EL1 before
>     entering the kernel.
>   else, which means VMSA unsupported and cannot boot Linux,
>     goto err_invalid_arch (dead loop).
> Else, no initialisation and keep the current EL before entering the
>   kernel.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> ---
>  arch/aarch64/boot.S            | 63 ++++++++++++++++++++++++++++++++--
>  arch/aarch64/include/asm/cpu.h | 10 ++++++
>  arch/aarch64/init.c            | 24 +++++++++++++
>  3 files changed, 94 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index 211077af17c8..b2b9863b8d6a 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -22,7 +22,8 @@
>  	 *   EL2 must be implemented.
>  	 *
>  	 * - EL2 (Non-secure)
> -	 *   Entering at EL2 is partially supported.
> +	 *   Entering at EL2 is partially supported for Armv8-A.
> +	 *   Entering at EL2 is supported for Armv8-R.
>  	 *   PSCI is not supported when entered in this exception level.
>  	 */
>  ASM_FUNC(_start)
> @@ -76,7 +77,50 @@ reset_at_el2:
>  	msr	sctlr_el2, x0
>  	isb
>  
> -	b	reset_no_el3
> +	/* Detect Armv8-R AArch64 */
> +	mrs	x1, id_aa64mmfr0_el1
> +	/*
> +	 * Check MSA, bits [51:48]:
> +	 * 0xf means Armv8-R AArch64.
> +	 * If not 0xf, proceed in Armv8-A EL2.
> +	 */
> +	ubfx	x0, x1, #48, #4			// MSA
> +	cmp	x0, 0xf
> +	bne	reset_no_el3
> +
> +	/*
> +	 * Armv8-R AArch64 is found, check if Linux can be booted.
> +	 * Check MSA_frac, bits [55:52]:
> +	 * 0x2 means EL1&0 translation regime also supports VMSAv8-64.
> +	 */
> +	ubfx	x0, x1, #52, #4			// MSA_frac
> +	cmp	x0, 0x2
> +	/*
> +	 * If not 0x2, no VMSA, so cannot boot Linux and dead loop.
> +	 * Also, since the architecture guarantees that those CPUID
> +	 * fields never lose features when the value in a field
> +	 * increases, we use blt to cover it.
> +	 */
> +	blt	err_invalid_arch

For the records: this part above is correct, compared against the Armv8-R
AArch64 ARM ARM supplement (DDI 0600A.c)

> +
> +	/* Start Armv8-R Linux at EL1 */
> +	mov	w0, #SPSR_KERNEL_EL1
> +	ldr	x1, =spsr_to_elx
> +	str	w0, [x1]
> +
> +	cpuid	x0, x1
> +	bl	find_logical_id
> +	cmp	x0, #MPIDR_INVALID
> +	b.eq	err_invalid_id
> +	bl	setup_stack
> +
> +	bl	cpu_init_bootwrapper
> +
> +	bl	cpu_init_armv8r_el2
> +
> +	bl	gic_secure_init

Do we actually need this? v8-R64 is always secure, so there is nothing
special that we'd need to do here? Have you tried dropping this?

Also this sequence looks like to have quite some overlap with the existing
code.
Can't we rewrite it like this:

	....
	blt	err_invalid_arch
	(set SPSR_KERNEL_EL1)

	bl	cpu_init_armv8r_el2

	b	reset_no_el3

and just find a solution for flag_keep_el?

> +
> +	b	start_bootmethod
>  
>  	/*
>  	 * EL1 initialization
> @@ -104,6 +148,7 @@ reset_no_el3:
>  	b	start_bootmethod
>  
>  err_invalid_id:
> +err_invalid_arch:
>  	b	.
>  
>  	/*
> @@ -121,10 +166,14 @@ ASM_FUNC(jump_kernel)
>  	ldr	x0, =SCTLR_EL1_KERNEL
>  	msr	sctlr_el1, x0
>  
> +	mrs	x5, CurrentEL
> +	cmp	x5, #CURRENTEL_EL2
> +	b.eq	1f
> +
>  	ldr	x0, =SCTLR_EL2_KERNEL
>  	msr	sctlr_el2, x0
>  
> -	cpuid	x0, x1
> +1:	cpuid	x0, x1
>  	bl	find_logical_id
>  	bl	setup_stack		// Reset stack pointer
>  
> @@ -147,10 +196,18 @@ ASM_FUNC(jump_kernel)
>  	 */
>  	bfi	x4, x19, #5, #1
>  
> +	mrs	x5, CurrentEL
> +	cmp	x5, #CURRENTEL_EL2
> +	b.eq	1f
> +
>  	msr	elr_el3, x19
>  	msr	spsr_el3, x4
>  	eret
>  
> +1:	msr	elr_el2, x19
> +	msr	spsr_el2, x4
> +	eret
> +
>  	.ltorg
>  
>  	.data
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 846b89f8405d..6b2f5fbe4502 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -58,7 +58,13 @@
>  #define SCR_EL3_TCR2EN			BIT(43)
>  #define SCR_EL3_PIEN			BIT(45)
>  
> +#define VTCR_EL2_MSA			BIT(31)
> +
>  #define HCR_EL2_RES1			BIT(1)
> +#define HCR_EL2_APK_NOTRAP		BIT(40)
> +#define HCR_EL2_API_NOTRAP		BIT(41)
> +#define HCR_EL2_FIEN_NOTRAP		BIT(47)
> +#define HCR_EL2_ENSCXT_NOTRAP	BIT(53)

That looks misaligned (checked in the file), you'd need two tabs.

>  #define ID_AA64DFR0_EL1_PMSVER		BITS(35, 32)
>  #define ID_AA64DFR0_EL1_TRACEBUFFER	BITS(47, 44)
> @@ -88,7 +94,9 @@
>  
>  #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
>  #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
> +#define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
>  #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
> +#define ID_AA64PFR0_EL1_CSV2	BITS(59, 56)

Same here, two tabs.

The bits and registers are correct, though.

>  #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
>  #define ID_AA64SMFR0_EL1_FA64		BIT(63)
> @@ -114,6 +122,7 @@
>  #define SPSR_I			(1 << 7)	/* IRQ masked */
>  #define SPSR_F			(1 << 6)	/* FIQ masked */
>  #define SPSR_T			(1 << 5)	/* Thumb */
> +#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
>  #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
>  #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
>  
> @@ -153,6 +162,7 @@
>  #else
>  #define SCTLR_EL1_KERNEL	SCTLR_EL1_RES1
>  #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
> +#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)

(that one is fine, btw, it just looks off in the diff)

>  #endif
>  
>  #ifndef __ASSEMBLY__
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index 37cb45fde446..8006f2705193 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -145,6 +145,30 @@ void cpu_init_el3(void)
>  	msr(CNTFRQ_EL0, COUNTER_FREQ);
>  }
>  
> +void cpu_init_armv8r_el2(void)
> +{
> +	unsigned long hcr = mrs(hcr_el2);
> +
> +	msr(vpidr_el2, mrs(midr_el1));
> +	msr(vmpidr_el2, mrs(mpidr_el1));
> +
> +	/* VTCR_MSA: VMSAv8-64 support */
> +	msr(vtcr_el2, VTCR_EL2_MSA);
> +
> +	if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2)

What is the significance of "<= 2"? Shall this read ">= 2"?

> +		hcr |= HCR_EL2_ENSCXT_NOTRAP;
> +
> +	if (mrs_field(ID_AA64PFR0_EL1, RAS) <= 2)

Same here, FEAT_RASv1p1 is 0b0010, so it should be ">= 2"?

Cheers,
Andre


> +		hcr |= HCR_EL2_FIEN_NOTRAP;
> +
> +	if (cpu_has_pauth())
> +		hcr |= HCR_EL2_APK_NOTRAP | HCR_EL2_API_NOTRAP;
> +
> +	msr(hcr_el2, hcr);
> +	isb();
> +	msr(CNTFRQ_EL0, COUNTER_FREQ);
> +}
> +
>  #ifdef PSCI
>  extern char psci_vectors[];
>  

Re: [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:28 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

Hi,

> When bootwrapper is compiled with Xen support and it is started
> at EL2 on Armv8-R AArch64, keep the current EL and jump to the
> Xen image.
> 
> Additionally, don't permit the usage of hvc conduit when Xen
> kernel is passed, because it's not supported.

Mmh, but this is unrelated to v8R, isn't it?
And I am not sure there is too much merit in checking this here?
After all PSCI *could* be triggered like this from EL2 (to EL2) in the
future, even if the *current* Xen implementation does not support this.

> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> ---
>  Makefile.am         | 1 +
>  arch/aarch64/boot.S | 7 +++++++
>  configure.ac        | 3 +++
>  3 files changed, 11 insertions(+)
> 
> diff --git a/Makefile.am b/Makefile.am
> index 34fbfb1f4ff8..bafce34682c3 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -112,6 +112,7 @@ XEN_CHOSEN	:= xen,xen-bootargs = \"$(XEN_CMDLINE)\";		\
>  			compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \
>  			reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>;	\
>  		   };
> +DEFINES		+= -DXEN
>  endif
>  
>  if INITRD
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index b2b9863b8d6a..0b30b82ad6d9 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -88,6 +88,7 @@ reset_at_el2:
>  	cmp	x0, 0xf
>  	bne	reset_no_el3
>  
> +#if !defined(XEN)
>  	/*
>  	 * Armv8-R AArch64 is found, check if Linux can be booted.

Does Xen equally rely on VMSA in EL1? Or does it not care, and just
leaves the EL1 setup totally to the guest? Supporting PMSA guests
as well?
Just asking to check whether the !XEN part would be in the right place
then.

>  	 * Check MSA_frac, bits [55:52]:
> @@ -107,6 +108,12 @@ reset_at_el2:
>  	mov	w0, #SPSR_KERNEL_EL1
>  	ldr	x1, =spsr_to_elx
>  	str	w0, [x1]
> +#else
> +	/* Start XEN on Armv8-R at EL2 */
> +	mov	w0, #1
> +	ldr	x1, =flag_keep_el
> +	str	w0, [x1]
> +#endif
>  
>  	cpuid	x0, x1
>  	bl	find_logical_id
> diff --git a/configure.ac b/configure.ac
> index 44459a4c849e..a5175db4148a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
>  AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
>  	[AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
>  )
> +AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"],
> +	[AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])]
> +)

As mentioned above, I am not sure this is too helpful.

Cheers,
Andre

>  AC_SUBST([PSCI_METHOD], [$USE_PSCI])
>  
>  # Allow a user to pass --with-initrd

Re: [boot-wrapper 6/7] aarch64: Support PSCI for Armv8-R AArch64

[Andre Przywara]

On Thu,  6 Jun 2024 14:36:27 +0100
Luca Fancellu <luca.fancellu@arm.com> wrote:

Hi,

> Add support for PSCI when booting Linux on Armv8-R AArch64,
> allow the autoconf parameter --enable-psci to take an argument
> which is the conduit to be used, it can be empty or 'smc' to
> select the smc conduit, it can be 'hvc' for the hvc conduit.

I am not super happy about this *build time* option, but I think the
alternatives are worse, and it keeps the code much simpler and cleaner:

> Depending on the selected conduit, the vector table will be
> installed on the VBAR_EL3 or VBAR_EL2 register.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
>  Makefile.am         |  5 ++++-
>  arch/aarch64/init.c | 15 ++++++++++++---
>  configure.ac        | 16 +++++++++++-----
>  3 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/Makefile.am b/Makefile.am
> index 6ebece25b230..34fbfb1f4ff8 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -49,11 +49,14 @@ endif
>  
>  if PSCI
>  DEFINES		+= -DPSCI
> +if PSCI_HVC
> +DEFINES		+= -DPSCI_HVC
> +endif
>  ARCH_OBJ	+= psci.o
>  COMMON_OBJ	+= psci.o
>  PSCI_NODE	:= psci {				\
>  			compatible = \"arm,psci\";	\
> -			method = \"smc\";		\
> +			method = \"$(PSCI_METHOD)\";	\
>  			cpu_on = <$(PSCI_CPU_ON)>;	\
>  			cpu_off = <$(PSCI_CPU_OFF)>;	\
>  		   };
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index 8006f2705193..3305e69270a4 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -174,10 +174,19 @@ extern char psci_vectors[];
>  
>  bool cpu_init_psci_arch(void)
>  {
> -	if (mrs(CurrentEL) != CURRENTEL_EL3)
> +	switch (mrs(CurrentEL)) {
> +#if !defined(PSCI_HVC)
> +	case CURRENTEL_EL3:
> +		msr(VBAR_EL3, (unsigned long)psci_vectors);
> +		break;
> +#else
> +	case CURRENTEL_EL2:
> +		msr(VBAR_EL2, (unsigned long)psci_vectors);
> +		break;
> +#endif
> +	default:
>  		return false;
> -
> -	msr(VBAR_EL3, (unsigned long)psci_vectors);
> +	}
>  	isb();
>  
>  	return true;
> diff --git a/configure.ac b/configure.ac
> index 9e3b7226cd69..44459a4c849e 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -83,13 +83,19 @@ AS_IF([test "x$X_IMAGE" != "x"],
>  # Allow a user to pass --enable-psci
>  AC_ARG_ENABLE([psci],
>  	AS_HELP_STRING([--disable-psci], [disable the psci boot method]),
> -	[USE_PSCI=$enableval], [USE_PSCI="yes"])
> -AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"])
> -AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no])
> -
> -AS_IF([test "x$USE_PSCI" != "xyes" -a "x$KERNEL_ES" = "x32"],
> +	[case "${enableval}" in
> +		yes|smc) USE_PSCI=smc ;;
> +		hvc) USE_PSCI=hvc ;;
> +		no) ;;
> +		*) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;;
> +	esac])
> +AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"])
> +AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
> +
> +AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
>  	[AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
>  )
> +AC_SUBST([PSCI_METHOD], [$USE_PSCI])
>  
>  # Allow a user to pass --with-initrd
>  AC_ARG_WITH([initrd],

Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Luca Fancellu]

Hi Andre,

> 
>> +
>> + /* Start Armv8-R Linux at EL1 */
>> + mov w0, #SPSR_KERNEL_EL1
>> + ldr x1, =spsr_to_elx
>> + str w0, [x1]
>> +
>> + cpuid x0, x1
>> + bl find_logical_id
>> + cmp x0, #MPIDR_INVALID
>> + b.eq err_invalid_id
>> + bl setup_stack
>> +
>> + bl cpu_init_bootwrapper
>> +
>> + bl cpu_init_armv8r_el2
>> +
>> + bl gic_secure_init
> 
> Do we actually need this? v8-R64 is always secure, so there is nothing
> special that we'd need to do here? Have you tried dropping this?
> 
> Also this sequence looks like to have quite some overlap with the existing
> code.
> Can't we rewrite it like this:
> 
> ....
> blt err_invalid_arch
> (set SPSR_KERNEL_EL1)
> 
> bl cpu_init_armv8r_el2
> 
> b reset_no_el3
> 
> and just find a solution for flag_keep_el?

What do you think about the below changes to be applied to this patch?

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index b2b9863b8d6a..2a8234f7a17d 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -108,19 +108,9 @@ reset_at_el2:
 	ldr	x1, =spsr_to_elx
 	str	w0, [x1]
 
-	cpuid	x0, x1
-	bl	find_logical_id
-	cmp	x0, #MPIDR_INVALID
-	b.eq	err_invalid_id
-	bl	setup_stack
-
-	bl	cpu_init_bootwrapper
-
 	bl	cpu_init_armv8r_el2
 
-	bl	gic_secure_init
-
-	b	start_bootmethod
+	b	reset_no_el3
 
 	/*
 	 * EL1 initialization
@@ -139,10 +129,16 @@ reset_no_el3:
 	b.eq	err_invalid_id
 	bl	setup_stack
 
+	ldr	w1, spsr_to_elx
+	and w0, w1, 0xf
+	cmp	w0, #SPSR_EL1H
+	b.eq drop_el
+
 	mov	w0, #1
 	ldr	x1, =flag_keep_el
 	str	w0, [x1]
 
+drop_el:
 	bl	cpu_init_bootwrapper
 
 	b	start_bootmethod


> 
>> +
>> + b start_bootmethod
>> 
>> /*
>> * EL1 initialization
>> @@ -104,6 +148,7 @@ reset_no_el3:
>> b start_bootmethod
>> 
>> err_invalid_id:
>> +err_invalid_arch:
>> b .
>> 
>> /*
>> @@ -121,10 +166,14 @@ ASM_FUNC(jump_kernel)
>> ldr x0, =SCTLR_EL1_KERNEL
>> msr sctlr_el1, x0
>> 
>> + mrs x5, CurrentEL
>> + cmp x5, #CURRENTEL_EL2
>> + b.eq 1f
>> +
>> ldr x0, =SCTLR_EL2_KERNEL
>> msr sctlr_el2, x0
>> 
>> - cpuid x0, x1
>> +1: cpuid x0, x1
>> bl find_logical_id
>> bl setup_stack // Reset stack pointer
>> 
>> @@ -147,10 +196,18 @@ ASM_FUNC(jump_kernel)
>> */
>> bfi x4, x19, #5, #1
>> 
>> + mrs x5, CurrentEL
>> + cmp x5, #CURRENTEL_EL2
>> + b.eq 1f
>> +
>> msr elr_el3, x19
>> msr spsr_el3, x4
>> eret
>> 
>> +1: msr elr_el2, x19
>> + msr spsr_el2, x4
>> + eret
>> +
>> .ltorg
>> 
>> .data
>> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
>> index 846b89f8405d..6b2f5fbe4502 100644
>> --- a/arch/aarch64/include/asm/cpu.h
>> +++ b/arch/aarch64/include/asm/cpu.h
>> @@ -58,7 +58,13 @@
>> #define SCR_EL3_TCR2EN BIT(43)
>> #define SCR_EL3_PIEN BIT(45)
>> 
>> +#define VTCR_EL2_MSA BIT(31)
>> +
>> #define HCR_EL2_RES1 BIT(1)
>> +#define HCR_EL2_APK_NOTRAP BIT(40)
>> +#define HCR_EL2_API_NOTRAP BIT(41)
>> +#define HCR_EL2_FIEN_NOTRAP BIT(47)
>> +#define HCR_EL2_ENSCXT_NOTRAP BIT(53)
> 
> That looks misaligned (checked in the file), you'd need two tabs.
> 
>> #define ID_AA64DFR0_EL1_PMSVER BITS(35, 32)
>> #define ID_AA64DFR0_EL1_TRACEBUFFER BITS(47, 44)
>> @@ -88,7 +94,9 @@
>> 
>> #define ID_AA64PFR1_EL1_MTE BITS(11, 8)
>> #define ID_AA64PFR1_EL1_SME BITS(27, 24)
>> +#define ID_AA64PFR0_EL1_RAS BITS(31, 28)
>> #define ID_AA64PFR0_EL1_SVE BITS(35, 32)
>> +#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56)
> 
> Same here, two tabs.
> 
> The bits and registers are correct, though.
> 
>> #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
>> #define ID_AA64SMFR0_EL1_FA64 BIT(63)
>> @@ -114,6 +122,7 @@
>> #define SPSR_I (1 << 7) /* IRQ masked */
>> #define SPSR_F (1 << 6) /* FIQ masked */
>> #define SPSR_T (1 << 5) /* Thumb */
>> +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */
>> #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */
>> #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */
>> 
>> @@ -153,6 +162,7 @@
>> #else
>> #define SCTLR_EL1_KERNEL SCTLR_EL1_RES1
>> #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
>> +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
> 
> (that one is fine, btw, it just looks off in the diff)

Thanks, I’ll fix all the alignments, probably some misconfiguration of my editor.

> 
>> #endif
>> 
>> #ifndef __ASSEMBLY__
>> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
>> index 37cb45fde446..8006f2705193 100644
>> --- a/arch/aarch64/init.c
>> +++ b/arch/aarch64/init.c
>> @@ -145,6 +145,30 @@ void cpu_init_el3(void)
>> msr(CNTFRQ_EL0, COUNTER_FREQ);
>> }
>> 
>> +void cpu_init_armv8r_el2(void)
>> +{
>> + unsigned long hcr = mrs(hcr_el2);
>> +
>> + msr(vpidr_el2, mrs(midr_el1));
>> + msr(vmpidr_el2, mrs(mpidr_el1));
>> +
>> + /* VTCR_MSA: VMSAv8-64 support */
>> + msr(vtcr_el2, VTCR_EL2_MSA);
>> +
>> + if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2)
> 
> What is the significance of "<= 2"? Shall this read ">= 2"?

I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:

1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)
2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)

Does it sounds ok for you?

> 
>> + hcr |= HCR_EL2_ENSCXT_NOTRAP;
>> +
>> + if (mrs_field(ID_AA64PFR0_EL1, RAS) <= 2)
> 
> Same here, FEAT_RASv1p1 is 0b0010, so it should be ">= 2"?

I’ll fix it.

Cheers,
Luca

Re: [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2

[Luca Fancellu]

Hi Andre,

> On 21 Jun 2024, at 11:36, Andre Przywara <Andre.Przywara@arm.com> wrote:
> 
> On Thu,  6 Jun 2024 14:36:28 +0100
> Luca Fancellu <luca.fancellu@arm.com> wrote:
> 
> Hi,
> 
>> When bootwrapper is compiled with Xen support and it is started
>> at EL2 on Armv8-R AArch64, keep the current EL and jump to the
>> Xen image.
>> 
>> Additionally, don't permit the usage of hvc conduit when Xen
>> kernel is passed, because it's not supported.
> 
> Mmh, but this is unrelated to v8R, isn't it?
> And I am not sure there is too much merit in checking this here?
> After all PSCI *could* be triggered like this from EL2 (to EL2) in the
> future, even if the *current* Xen implementation does not support this.

Yes, it’s only the current Xen implementation that doesn’t support this.

> 
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>> ---
>> Makefile.am         | 1 +
>> arch/aarch64/boot.S | 7 +++++++
>> configure.ac        | 3 +++
>> 3 files changed, 11 insertions(+)
>> 
>> diff --git a/Makefile.am b/Makefile.am
>> index 34fbfb1f4ff8..bafce34682c3 100644
>> --- a/Makefile.am
>> +++ b/Makefile.am
>> @@ -112,6 +112,7 @@ XEN_CHOSEN := xen,xen-bootargs = \"$(XEN_CMDLINE)\"; \
>> compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \
>> reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>; \
>>   };
>> +DEFINES += -DXEN
>> endif
>> 
>> if INITRD
>> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
>> index b2b9863b8d6a..0b30b82ad6d9 100644
>> --- a/arch/aarch64/boot.S
>> +++ b/arch/aarch64/boot.S
>> @@ -88,6 +88,7 @@ reset_at_el2:
>> cmp x0, 0xf
>> bne reset_no_el3
>> 
>> +#if !defined(XEN)
>> /*
>> * Armv8-R AArch64 is found, check if Linux can be booted.
> 
> Does Xen equally rely on VMSA in EL1? Or does it not care, and just
> leaves the EL1 setup totally to the guest? Supporting PMSA guests
> as well?
> Just asking to check whether the !XEN part would be in the right place
> then.

Xen does not care and it just leaves the EL1 setup to the guest.

> 
>> * Check MSA_frac, bits [55:52]:
>> @@ -107,6 +108,12 @@ reset_at_el2:
>> mov w0, #SPSR_KERNEL_EL1
>> ldr x1, =spsr_to_elx
>> str w0, [x1]
>> +#else
>> + /* Start XEN on Armv8-R at EL2 */
>> + mov w0, #1
>> + ldr x1, =flag_keep_el
>> + str w0, [x1]
>> +#endif
>> 
>> cpuid x0, x1
>> bl find_logical_id
>> diff --git a/configure.ac b/configure.ac
>> index 44459a4c849e..a5175db4148a 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
>> AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
>> [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
>> )
>> +AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"],
>> + [AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])]
>> +)
> 
> As mentioned above, I am not sure this is too helpful.

Ok, so your proposal is to remove this check, am I right?

Cheers,
Luca

Re: [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2

[Luca Fancellu]

Hi Andre,

> 
>> 
>>> * Check MSA_frac, bits [55:52]:
>>> @@ -107,6 +108,12 @@ reset_at_el2:
>>> mov w0, #SPSR_KERNEL_EL1
>>> ldr x1, =spsr_to_elx
>>> str w0, [x1]
>>> +#else
>>> + /* Start XEN on Armv8-R at EL2 */
>>> + mov w0, #1
>>> + ldr x1, =flag_keep_el
>>> + str w0, [x1]
>>> +#endif
>>> 
>>> cpuid x0, x1
>>> bl find_logical_id
>>> diff --git a/configure.ac b/configure.ac
>>> index 44459a4c849e..a5175db4148a 100644
>>> --- a/configure.ac
>>> +++ b/configure.ac
>>> @@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
>>> AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
>>> [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
>>> )
>>> +AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"],
>>> + [AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])]
>>> +)
>> 
>> As mentioned above, I am not sure this is too helpful.
> 
> Ok, so your proposal is to remove this check, am I right?

Gentle ping on this.

Cheers,
Luca

Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Luca Fancellu]

Hi Andre,


> On 24 Jun 2024, at 13:22, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
> 
> Hi Andre,
> 
>> 
>>> +
>>> + /* Start Armv8-R Linux at EL1 */
>>> + mov w0, #SPSR_KERNEL_EL1
>>> + ldr x1, =spsr_to_elx
>>> + str w0, [x1]
>>> +
>>> + cpuid x0, x1
>>> + bl find_logical_id
>>> + cmp x0, #MPIDR_INVALID
>>> + b.eq err_invalid_id
>>> + bl setup_stack
>>> +
>>> + bl cpu_init_bootwrapper
>>> +
>>> + bl cpu_init_armv8r_el2
>>> +
>>> + bl gic_secure_init
>> 
>> Do we actually need this? v8-R64 is always secure, so there is nothing
>> special that we'd need to do here? Have you tried dropping this?
>> 
>> Also this sequence looks like to have quite some overlap with the existing
>> code.
>> Can't we rewrite it like this:
>> 
>> ....
>> blt err_invalid_arch
>> (set SPSR_KERNEL_EL1)
>> 
>> bl cpu_init_armv8r_el2
>> 
>> b reset_no_el3
>> 
>> and just find a solution for flag_keep_el?
> 
> What do you think about the below changes to be applied to this patch?
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index b2b9863b8d6a..2a8234f7a17d 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -108,19 +108,9 @@ reset_at_el2:
> ldr x1, =spsr_to_elx
> str w0, [x1]
> 
> - cpuid x0, x1
> - bl find_logical_id
> - cmp x0, #MPIDR_INVALID
> - b.eq err_invalid_id
> - bl setup_stack
> -
> - bl cpu_init_bootwrapper
> -
> bl cpu_init_armv8r_el2
> 
> - bl gic_secure_init
> -
> - b start_bootmethod
> + b reset_no_el3
> 
> /*
> * EL1 initialization
> @@ -139,10 +129,16 @@ reset_no_el3:
> b.eq err_invalid_id
> bl setup_stack
> 
> + ldr w1, spsr_to_elx
> + and w0, w1, 0xf
> + cmp w0, #SPSR_EL1H
> + b.eq drop_el
> +
> mov w0, #1
> ldr x1, =flag_keep_el
> str w0, [x1]
> 
> +drop_el:
> bl cpu_init_bootwrapper
> 
> b start_bootmethod
> 
> 

Gentle ping on this...


>> 
>>> #endif
>>> 
>>> #ifndef __ASSEMBLY__
>>> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
>>> index 37cb45fde446..8006f2705193 100644
>>> --- a/arch/aarch64/init.c
>>> +++ b/arch/aarch64/init.c
>>> @@ -145,6 +145,30 @@ void cpu_init_el3(void)
>>> msr(CNTFRQ_EL0, COUNTER_FREQ);
>>> }
>>> 
>>> +void cpu_init_armv8r_el2(void)
>>> +{
>>> + unsigned long hcr = mrs(hcr_el2);
>>> +
>>> + msr(vpidr_el2, mrs(midr_el1));
>>> + msr(vmpidr_el2, mrs(mpidr_el1));
>>> +
>>> + /* VTCR_MSA: VMSAv8-64 support */
>>> + msr(vtcr_el2, VTCR_EL2_MSA);
>>> +
>>> + if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2)
>> 
>> What is the significance of "<= 2"? Shall this read ">= 2"?
> 
> I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
> FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:
> 
> 1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)
> 2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)
> 
> Does it sounds ok for you?

And this.

Cheers,
Luca

Re: [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2

[Andre Przywara]

On Mon, 24 Jun 2024 14:28:24 +0100
Luca Fancellu <Luca.Fancellu@arm.com> wrote:

> Hi Andre,
> 
> > On 21 Jun 2024, at 11:36, Andre Przywara <Andre.Przywara@arm.com> wrote:
> >
> > On Thu,  6 Jun 2024 14:36:28 +0100
> > Luca Fancellu <luca.fancellu@arm.com> wrote:
> >
> > Hi,
> >  
> >> When bootwrapper is compiled with Xen support and it is started
> >> at EL2 on Armv8-R AArch64, keep the current EL and jump to the
> >> Xen image.
> >>
> >> Additionally, don't permit the usage of hvc conduit when Xen
> >> kernel is passed, because it's not supported.  
> >
> > Mmh, but this is unrelated to v8R, isn't it?
> > And I am not sure there is too much merit in checking this here?
> > After all PSCI *could* be triggered like this from EL2 (to EL2) in the
> > future, even if the *current* Xen implementation does not support this.  
> 
> Yes, it’s only the current Xen implementation that doesn’t support this.
> 
> >  
> >> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> >> ---
> >> Makefile.am         | 1 +
> >> arch/aarch64/boot.S | 7 +++++++
> >> configure.ac        | 3 +++
> >> 3 files changed, 11 insertions(+)
> >>
> >> diff --git a/Makefile.am b/Makefile.am
> >> index 34fbfb1f4ff8..bafce34682c3 100644
> >> --- a/Makefile.am
> >> +++ b/Makefile.am
> >> @@ -112,6 +112,7 @@ XEN_CHOSEN := xen,xen-bootargs = \"$(XEN_CMDLINE)\"; \
> >> compatible = \"xen,linux-zimage\", \"xen,multiboot-module\"; \
> >> reg = <0x0 $(DOM0_OFFSET) 0x0 $(KERNEL_SIZE)>; \
> >>   };
> >> +DEFINES += -DXEN
> >> endif
> >>
> >> if INITRD
> >> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> >> index b2b9863b8d6a..0b30b82ad6d9 100644
> >> --- a/arch/aarch64/boot.S
> >> +++ b/arch/aarch64/boot.S
> >> @@ -88,6 +88,7 @@ reset_at_el2:
> >> cmp x0, 0xf
> >> bne reset_no_el3
> >>
> >> +#if !defined(XEN)
> >> /*
> >> * Armv8-R AArch64 is found, check if Linux can be booted.  
> >
> > Does Xen equally rely on VMSA in EL1? Or does it not care, and just
> > leaves the EL1 setup totally to the guest? Supporting PMSA guests
> > as well?
> > Just asking to check whether the !XEN part would be in the right place
> > then.  
> 
> Xen does not care and it just leaves the EL1 setup to the guest.
> 
> >  
> >> * Check MSA_frac, bits [55:52]:
> >> @@ -107,6 +108,12 @@ reset_at_el2:
> >> mov w0, #SPSR_KERNEL_EL1
> >> ldr x1, =spsr_to_elx
> >> str w0, [x1]
> >> +#else
> >> + /* Start XEN on Armv8-R at EL2 */
> >> + mov w0, #1
> >> + ldr x1, =flag_keep_el
> >> + str w0, [x1]
> >> +#endif
> >>
> >> cpuid x0, x1
> >> bl find_logical_id
> >> diff --git a/configure.ac b/configure.ac
> >> index 44459a4c849e..a5175db4148a 100644
> >> --- a/configure.ac
> >> +++ b/configure.ac
> >> @@ -95,6 +95,9 @@ AM_CONDITIONAL([PSCI_HVC], [test "x$USE_PSCI" = "xhvc"])
> >> AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
> >> [AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
> >> )
> >> +AS_IF([test "x$USE_PSCI" = "xhvc" -a "x$X_IMAGE" != "x"],
> >> + [AC_MSG_ERROR([With Xen kernel, PSCI conduit must be smc.])]
> >> +)  
> >
> > As mentioned above, I am not sure this is too helpful.  
> 
> Ok, so your proposal is to remove this check, am I right?

Yes, I think this is overzealous.

Cheers,
Andre

Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Mon, 24 Jun 2024 13:22:38 +0100
Luca Fancellu <Luca.Fancellu@arm.com> wrote:

Hi Luca,

> Hi Andre,
> 
> >  
> >> +
> >> + /* Start Armv8-R Linux at EL1 */
> >> + mov w0, #SPSR_KERNEL_EL1
> >> + ldr x1, =spsr_to_elx
> >> + str w0, [x1]
> >> +
> >> + cpuid x0, x1
> >> + bl find_logical_id
> >> + cmp x0, #MPIDR_INVALID
> >> + b.eq err_invalid_id
> >> + bl setup_stack
> >> +
> >> + bl cpu_init_bootwrapper
> >> +
> >> + bl cpu_init_armv8r_el2
> >> +
> >> + bl gic_secure_init  
> >
> > Do we actually need this? v8-R64 is always secure, so there is nothing
> > special that we'd need to do here? Have you tried dropping this?
> >
> > Also this sequence looks like to have quite some overlap with the existing
> > code.
> > Can't we rewrite it like this:
> >
> > ....
> > blt err_invalid_arch
> > (set SPSR_KERNEL_EL1)
> >
> > bl cpu_init_armv8r_el2
> >
> > b reset_no_el3
> >
> > and just find a solution for flag_keep_el?  
> 
> What do you think about the below changes to be applied to this patch?

A patch to a patch is really hard to read, please send a new version with
your proposal.

> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index b2b9863b8d6a..2a8234f7a17d 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -108,19 +108,9 @@ reset_at_el2:
>         ldr     x1, =spsr_to_elx
>         str     w0, [x1]
> 
> -       cpuid   x0, x1
> -       bl      find_logical_id
> -       cmp     x0, #MPIDR_INVALID
> -       b.eq    err_invalid_id
> -       bl      setup_stack
> -
> -       bl      cpu_init_bootwrapper
> -
>         bl      cpu_init_armv8r_el2
> 
> -       bl      gic_secure_init
> -
> -       b       start_bootmethod
> +       b       reset_no_el3
> 
>         /*
>          * EL1 initialization
> @@ -139,10 +129,16 @@ reset_no_el3:
>         b.eq    err_invalid_id
>         bl      setup_stack
> 
> +       ldr     w1, spsr_to_elx
> +       and w0, w1, 0xf
> +       cmp     w0, #SPSR_EL1H
> +       b.eq drop_el
> +
>         mov     w0, #1
>         ldr     x1, =flag_keep_el
>         str     w0, [x1]
> 
> +drop_el:
>         bl      cpu_init_bootwrapper
> 
>         b       start_bootmethod
> 
> 
> >  
> >> +
> >> + b start_bootmethod
> >>
> >> /*
> >> * EL1 initialization
> >> @@ -104,6 +148,7 @@ reset_no_el3:
> >> b start_bootmethod
> >>
> >> err_invalid_id:
> >> +err_invalid_arch:
> >> b .
> >>
> >> /*
> >> @@ -121,10 +166,14 @@ ASM_FUNC(jump_kernel)
> >> ldr x0, =SCTLR_EL1_KERNEL
> >> msr sctlr_el1, x0
> >>
> >> + mrs x5, CurrentEL
> >> + cmp x5, #CURRENTEL_EL2
> >> + b.eq 1f
> >> +
> >> ldr x0, =SCTLR_EL2_KERNEL
> >> msr sctlr_el2, x0
> >>
> >> - cpuid x0, x1
> >> +1: cpuid x0, x1
> >> bl find_logical_id
> >> bl setup_stack // Reset stack pointer
> >>
> >> @@ -147,10 +196,18 @@ ASM_FUNC(jump_kernel)
> >> */
> >> bfi x4, x19, #5, #1
> >>
> >> + mrs x5, CurrentEL
> >> + cmp x5, #CURRENTEL_EL2
> >> + b.eq 1f
> >> +
> >> msr elr_el3, x19
> >> msr spsr_el3, x4
> >> eret
> >>
> >> +1: msr elr_el2, x19
> >> + msr spsr_el2, x4
> >> + eret
> >> +
> >> .ltorg
> >>
> >> .data
> >> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> >> index 846b89f8405d..6b2f5fbe4502 100644
> >> --- a/arch/aarch64/include/asm/cpu.h
> >> +++ b/arch/aarch64/include/asm/cpu.h
> >> @@ -58,7 +58,13 @@
> >> #define SCR_EL3_TCR2EN BIT(43)
> >> #define SCR_EL3_PIEN BIT(45)
> >>
> >> +#define VTCR_EL2_MSA BIT(31)
> >> +
> >> #define HCR_EL2_RES1 BIT(1)
> >> +#define HCR_EL2_APK_NOTRAP BIT(40)
> >> +#define HCR_EL2_API_NOTRAP BIT(41)
> >> +#define HCR_EL2_FIEN_NOTRAP BIT(47)
> >> +#define HCR_EL2_ENSCXT_NOTRAP BIT(53)  
> >
> > That looks misaligned (checked in the file), you'd need two tabs.
> >  
> >> #define ID_AA64DFR0_EL1_PMSVER BITS(35, 32)
> >> #define ID_AA64DFR0_EL1_TRACEBUFFER BITS(47, 44)
> >> @@ -88,7 +94,9 @@
> >>
> >> #define ID_AA64PFR1_EL1_MTE BITS(11, 8)
> >> #define ID_AA64PFR1_EL1_SME BITS(27, 24)
> >> +#define ID_AA64PFR0_EL1_RAS BITS(31, 28)
> >> #define ID_AA64PFR0_EL1_SVE BITS(35, 32)
> >> +#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56)  
> >
> > Same here, two tabs.
> >
> > The bits and registers are correct, though.
> >  
> >> #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
> >> #define ID_AA64SMFR0_EL1_FA64 BIT(63)
> >> @@ -114,6 +122,7 @@
> >> #define SPSR_I (1 << 7) /* IRQ masked */
> >> #define SPSR_F (1 << 6) /* FIQ masked */
> >> #define SPSR_T (1 << 5) /* Thumb */
> >> +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */
> >> #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */
> >> #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */
> >>
> >> @@ -153,6 +162,7 @@
> >> #else
> >> #define SCTLR_EL1_KERNEL SCTLR_EL1_RES1
> >> #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
> >> +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)  
> >
> > (that one is fine, btw, it just looks off in the diff)  
> 
> Thanks, I’ll fix all the alignments, probably some misconfiguration of my editor.
> 
> >  
> >> #endif
> >>
> >> #ifndef __ASSEMBLY__
> >> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> >> index 37cb45fde446..8006f2705193 100644
> >> --- a/arch/aarch64/init.c
> >> +++ b/arch/aarch64/init.c
> >> @@ -145,6 +145,30 @@ void cpu_init_el3(void)
> >> msr(CNTFRQ_EL0, COUNTER_FREQ);
> >> }
> >>
> >> +void cpu_init_armv8r_el2(void)
> >> +{
> >> + unsigned long hcr = mrs(hcr_el2);
> >> +
> >> + msr(vpidr_el2, mrs(midr_el1));
> >> + msr(vmpidr_el2, mrs(mpidr_el1));
> >> +
> >> + /* VTCR_MSA: VMSAv8-64 support */
> >> + msr(vtcr_el2, VTCR_EL2_MSA);
> >> +
> >> + if (mrs_field(ID_AA64PFR0_EL1, CSV2) <= 2)  
> >
> > What is the significance of "<= 2"? Shall this read ">= 2"?  
> 
> I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
> FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:
> 
> 1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)

... or larger than 2, since CSV2_3 includes all functionality of CSV2_2.

> 2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)

... and ID_AA64PFR0_EL1.CSV2 is 0b0001. Also I think CSV2_frac >= 0b0010.

> Does it sounds ok for you?

Before this gets too complicated, please check two things:
1) HCR_EL2.EnSCXT is RES0 otherwise, which means we can always write this
unconditionally, without adverse effects?
2) The Armv8-R64 supplement defines minimum values for PFR0.CSV2, maybe
this simplifies some checks?

Cheers,
Andre

> >> + hcr |= HCR_EL2_ENSCXT_NOTRAP;
> >> +
> >> + if (mrs_field(ID_AA64PFR0_EL1, RAS) <= 2)  
> >
> > Same here, FEAT_RASv1p1 is 0b0010, so it should be ">= 2"?  
> 
> I’ll fix it.
> 
> Cheers,
> Luca
> 
> 

Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Luca Fancellu]

Hi Andre,

> 
> A patch to a patch is really hard to read, please send a new version with
> your proposal.

Sure I will.

>>> 
>> 
>> I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
>> FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:
>> 
>> 1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)
> 
> ... or larger than 2, since CSV2_3 includes all functionality of CSV2_2.
> 
>> 2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)
> 
> ... and ID_AA64PFR0_EL1.CSV2 is 0b0001. Also I think CSV2_frac >= 0b0010.
> 
>> Does it sounds ok for you?
> 
> Before this gets too complicated, please check two things:
> 1) HCR_EL2.EnSCXT is RES0 otherwise, which means we can always write this
> unconditionally, without adverse effects?

Yes, HCR_EL2.EnSCXT is RES0 otherwise, I guess that if we write 1 when it is not implemented, it is ignored? And
for the cases where it is implemented, then 1 would be the right value.
Would it be the right approach? I’ve always avoided to write on reserved fields.

> 2) The Armv8-R64 supplement defines minimum values for PFR0.CSV2, maybe
> this simplifies some checks?

I checked but it doesn’t simplifies, so I think I should do:

if ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 2) ||
    ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 1) && (mrs_field(ID_AA64PFR1_EL1, CSV2_frac) >= 2)))
    hcr |= HCR_EL2_ENSCXT_NOTRAP;

Please let me know your preference.

Cheers,
Luca

> 
> Cheers,
> Andre

Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Tue, 16 Jul 2024 14:33:08 +0100
Luca Fancellu <Luca.Fancellu@arm.com> wrote:

Hi Luca,

> > A patch to a patch is really hard to read, please send a new version with
> > your proposal.  
> 
> Sure I will.
> 
> >>>  
> >>
> >> I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
> >> FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:
> >>
> >> 1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)  
> >
> > ... or larger than 2, since CSV2_3 includes all functionality of CSV2_2.
> >  
> >> 2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)  
> >
> > ... and ID_AA64PFR0_EL1.CSV2 is 0b0001. Also I think CSV2_frac >= 0b0010.
> >  
> >> Does it sounds ok for you?  
> >
> > Before this gets too complicated, please check two things:
> > 1) HCR_EL2.EnSCXT is RES0 otherwise, which means we can always write this
> > unconditionally, without adverse effects?  
> 
> Yes, HCR_EL2.EnSCXT is RES0 otherwise, I guess that if we write 1 when it is not implemented, it is ignored? And
> for the cases where it is implemented, then 1 would be the right value.
> Would it be the right approach? I’ve always avoided to write on reserved fields.

Yeah, I agree it leaves some bitter taste, though the definition of RES0
in the glossary seems to suggest it's safe to do.
In this particular case, which is confined to v8-R64, which implements at
least some kind of CSV2, I personally tend to set HCR_EL2.EnSCXT
unconditionally, accompanied by a comment why it is safe to do so.

Cheers,
Andre

> > 2) The Armv8-R64 supplement defines minimum values for PFR0.CSV2, maybe
> > this simplifies some checks?  
> 
> I checked but it doesn’t simplifies, so I think I should do:
> 
> if ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 2) ||
>     ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 1) && (mrs_field(ID_AA64PFR1_EL1, CSV2_frac) >= 2)))
>     hcr |= HCR_EL2_ENSCXT_NOTRAP;
> 
> Please let me know your preference.
> 
> Cheers,
> Luca
> 
> >
> > Cheers,
> > Andre  
>