* [PATCH 0/2] Add support for Xilinx XDMA Soft IP as Root Port
@ 2024-06-24 10:42 Thippeswamy Havalige
2024-06-24 10:42 ` [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige
2024-06-24 10:42 ` [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige
0 siblings, 2 replies; 5+ messages in thread
From: Thippeswamy Havalige @ 2024-06-24 10:42 UTC (permalink / raw)
To: bhelgaas, kw, robh, krzk+dt, conor+dt, lpieralisi
Cc: linux-pci, devicetree, linux-kernel, michal.simek,
linux-arm-kernel, bharat.kumar.gogada, Thippeswamy Havalige
This series of patch add support for Xilinx QDMA Soft IP as Root Port.
The Xilinx QDMA Soft IP support's 32 bit and 64bit BAR's.
As Root Port it supports MSI and legacy interrupts.
Thippeswamy Havalige (2):
dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root
Port Bridge
PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver
.../devicetree/bindings/pci/xlnx,xdma-host.yaml | 41 +++++++++++++++-
drivers/pci/controller/pcie-xilinx-dma-pl.c | 56 ++++++++++++++++++++--
2 files changed, 92 insertions(+), 5 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-06-24 10:42 [PATCH 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige @ 2024-06-24 10:42 ` Thippeswamy Havalige 2024-06-24 11:24 ` Rob Herring (Arm) 2024-06-24 10:42 ` [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige 1 sibling, 1 reply; 5+ messages in thread From: Thippeswamy Havalige @ 2024-06-24 10:42 UTC (permalink / raw) To: bhelgaas, kw, robh, krzk+dt, conor+dt, lpieralisi Cc: linux-pci, devicetree, linux-kernel, michal.simek, linux-arm-kernel, bharat.kumar.gogada, Thippeswamy Havalige Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 2f59b3a..b705e47 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -14,10 +14,21 @@ allOf: properties: compatible: - const: xlnx,xdma-host-3.00 + enum: + - xlnx,xdma-host-3.00 + - xlnx,qdma-host-3.00 reg: - maxItems: 1 + items: + - description: configuration region and XDMA bridge register. + - description: QDMA bridge register. + minItems: 1 + + reg-names: + items: + - const: cfg + - const: breg + minItems: 1 ranges: maxItems: 2 @@ -111,4 +122,30 @@ examples: interrupt-controller; }; }; + + axi-pcie@80000000 { + compatible = "xlnx,qdma-host-3.00"; + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>; + reg-names = "cfg", "breg"; + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge 2024-06-24 10:42 ` [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige @ 2024-06-24 11:24 ` Rob Herring (Arm) 0 siblings, 0 replies; 5+ messages in thread From: Rob Herring (Arm) @ 2024-06-24 11:24 UTC (permalink / raw) To: Thippeswamy Havalige Cc: linux-arm-kernel, conor+dt, bharat.kumar.gogada, krzk+dt, devicetree, michal.simek, lpieralisi, kw, bhelgaas, linux-kernel, linux-pci On Mon, 24 Jun 2024 16:12:38 +0530, Thippeswamy Havalige wrote: > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > --- > .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++++-- > 1 file changed, 39 insertions(+), 2 deletions(-) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dts:55.31-79.15: Warning (pci_bridge): /example-0/soc/axi-pcie@80000000: node name is not "pci" or "pcie" Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dtb: Warning (unit_address_format): Failed prerequisite 'pci_bridge' Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dtb: Warning (pci_device_reg): Failed prerequisite 'pci_bridge' Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge' /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dtb: axi-pcie@80000000: $nodename:0: 'axi-pcie@80000000' does not match '^pcie?@' from schema $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/xlnx,xdma-host.example.dtb: axi-pcie@80000000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type' were unexpected) from schema $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240624104239.132159-2-thippesw@amd.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver 2024-06-24 10:42 [PATCH 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige 2024-06-24 10:42 ` [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige @ 2024-06-24 10:42 ` Thippeswamy Havalige 2024-06-26 20:07 ` kernel test robot 1 sibling, 1 reply; 5+ messages in thread From: Thippeswamy Havalige @ 2024-06-24 10:42 UTC (permalink / raw) To: bhelgaas, kw, robh, krzk+dt, conor+dt, lpieralisi Cc: linux-pci, devicetree, linux-kernel, michal.simek, linux-arm-kernel, bharat.kumar.gogada, Thippeswamy Havalige Add support for Xilinx QDMA Soft IP core as Root Port. The versal prime devices support QDMA soft IP module in programmable logic. The integrated QDMA Soft IP block has integrated bridge function that can act as PCIe Root Port. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- drivers/pci/controller/pcie-xilinx-dma-pl.c | 56 +++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-dma-pl.c b/drivers/pci/controller/pcie-xilinx-dma-pl.c index 5be5dfd..11ba656 100644 --- a/drivers/pci/controller/pcie-xilinx-dma-pl.c +++ b/drivers/pci/controller/pcie-xilinx-dma-pl.c @@ -13,6 +13,7 @@ #include <linux/msi.h> #include <linux/of_address.h> #include <linux/of_pci.h> +#include <linux/of_platform.h> #include "../pci.h" #include "pcie-xilinx-common.h" @@ -71,10 +72,24 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11) +#define QDMA_BRIDGE_BASE_OFF 0xCD8 /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 64 +enum xilinx_pl_dma_version { + XDMA, + QDMA, +}; + +/** + * struct xilinx_pl_dma_variant - CPM variant information + * @version: DMA version + */ +struct xilinx_pl_dma_variant { + enum xilinx_pl_dma_version version; +}; + struct xilinx_msi { struct irq_domain *msi_domain; unsigned long *bitmap; @@ -101,6 +116,7 @@ struct xilinx_msi { struct pl_dma_pcie { struct device *dev; void __iomem *reg_base; + void __iomem *cfg_base; int irq; struct pci_config_window *cfg; phys_addr_t phys_reg_base; @@ -110,16 +126,23 @@ struct pl_dma_pcie { struct xilinx_msi msi; int intx_irq; raw_spinlock_t lock; + const struct xilinx_pl_dma_variant *variant; }; static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) { - return readl(port->reg_base + reg); + if (port->variant->version == XDMA) + return readl(port->reg_base + reg); + else + return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); } static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg) { - writel(val, port->reg_base + reg); + if (port->variant->version == XDMA) + writel(val, port->reg_base + reg); + else + writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); } static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port) @@ -173,7 +196,10 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus, if (!xilinx_pl_dma_pcie_valid_device(bus, devfn)) return NULL; - return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + if (port->variant->version == XDMA) + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + else + return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ @@ -731,6 +757,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port, port->reg_base = port->cfg->win; + if (port->variant->version == QDMA) { + port->cfg_base = port->cfg->win; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); + port->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(port->reg_base)) + return PTR_ERR(port->reg_base); + port->phys_reg_base = res->start; + } + err = xilinx_request_msi_irq(port); if (err) { pci_ecam_free(port->cfg); @@ -760,6 +795,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) if (!bus) return -ENODEV; + port->variant = of_device_get_match_data(dev); + err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -791,9 +828,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) return err; } +static const struct xilinx_pl_dma_variant xdma_host = { + .version = XDMA, +}; + +static const struct xilinx_pl_dma_variant qdma_host = { + .version = QDMA, +}; + static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = { { .compatible = "xlnx,xdma-host-3.00", + .data = &xdma_host, + }, + { + .compatible = "xlnx,qdma-host-3.00", + .data = &qdma_host, }, {} }; -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver 2024-06-24 10:42 ` [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige @ 2024-06-26 20:07 ` kernel test robot 0 siblings, 0 replies; 5+ messages in thread From: kernel test robot @ 2024-06-26 20:07 UTC (permalink / raw) To: Thippeswamy Havalige, bhelgaas, kw, robh, krzk+dt, conor+dt, lpieralisi Cc: oe-kbuild-all, linux-pci, devicetree, linux-kernel, michal.simek, linux-arm-kernel, bharat.kumar.gogada, Thippeswamy Havalige Hi Thippeswamy, kernel test robot noticed the following build warnings: [auto build test WARNING on pci/next] [also build test WARNING on pci/for-linus linus/master v6.10-rc5 next-20240625] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Thippeswamy-Havalige/dt-bindings-PCI-xilinx-xdma-Add-schemas-for-Xilinx-QDMA-PCIe-Root-Port-Bridge/20240626-052852 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240624104239.132159-3-thippesw%40amd.com patch subject: [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406270344.9nOuTH5k-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'cfg_base' not described in 'pl_dma_pcie' >> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'variant' not described in 'pl_dma_pcie' vim +130 drivers/pci/controller/pcie-xilinx-dma-pl.c 8d786149d78c77 Thippeswamy Havalige 2023-10-03 101 8d786149d78c77 Thippeswamy Havalige 2023-10-03 102 /** 8d786149d78c77 Thippeswamy Havalige 2023-10-03 103 * struct pl_dma_pcie - PCIe port information 8d786149d78c77 Thippeswamy Havalige 2023-10-03 104 * @dev: Device pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 105 * @reg_base: IO Mapped Register Base 8d786149d78c77 Thippeswamy Havalige 2023-10-03 106 * @irq: Interrupt number 8d786149d78c77 Thippeswamy Havalige 2023-10-03 107 * @cfg: Holds mappings of config space window 8d786149d78c77 Thippeswamy Havalige 2023-10-03 108 * @phys_reg_base: Physical address of reg base 8d786149d78c77 Thippeswamy Havalige 2023-10-03 109 * @intx_domain: Legacy IRQ domain pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 110 * @pldma_domain: PL DMA IRQ domain pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 111 * @resources: Bus Resources 8d786149d78c77 Thippeswamy Havalige 2023-10-03 112 * @msi: MSI information 8d786149d78c77 Thippeswamy Havalige 2023-10-03 113 * @intx_irq: INTx error interrupt number 8d786149d78c77 Thippeswamy Havalige 2023-10-03 114 * @lock: Lock protecting shared register access 8d786149d78c77 Thippeswamy Havalige 2023-10-03 115 */ 8d786149d78c77 Thippeswamy Havalige 2023-10-03 116 struct pl_dma_pcie { 8d786149d78c77 Thippeswamy Havalige 2023-10-03 117 struct device *dev; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 118 void __iomem *reg_base; 21ff31dc400101 Thippeswamy Havalige 2024-06-24 119 void __iomem *cfg_base; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 120 int irq; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 121 struct pci_config_window *cfg; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 122 phys_addr_t phys_reg_base; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 123 struct irq_domain *intx_domain; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 124 struct irq_domain *pldma_domain; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 125 struct list_head resources; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 126 struct xilinx_msi msi; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 127 int intx_irq; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 128 raw_spinlock_t lock; 21ff31dc400101 Thippeswamy Havalige 2024-06-24 129 const struct xilinx_pl_dma_variant *variant; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 @130 }; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 131 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-06-26 20:08 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-24 10:42 [PATCH 0/2] Add support for Xilinx XDMA Soft IP as Root Port Thippeswamy Havalige 2024-06-24 10:42 ` [PATCH 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Thippeswamy Havalige 2024-06-24 11:24 ` Rob Herring (Arm) 2024-06-24 10:42 ` [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Thippeswamy Havalige 2024-06-26 20:07 ` kernel test robot
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