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From: Anand Moon <linux.amoon@gmail.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>
Cc: Anand Moon <linux.amoon@gmail.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH linu-next v1] PCI: dw-rockchip: Enable async probe by default
Date: Tue, 25 Jun 2024 21:27:57 +0530	[thread overview]
Message-ID: <20240625155759.132878-1-linux.amoon@gmail.com> (raw)

Rockchip PCIe driver lets waits for the combo PHY link like PCIe 3.0,
PCIe 2.0 and SATA 3.0 controller to be up during the probe this
consumes several milliseconds during boot.

Establishing a PCIe link can take a while; allow asynchronous probing so
that link establishment can happen in the background while other devices
are being probed.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 61b1acba7182..74a3e9d172a0 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -367,6 +367,7 @@ static struct platform_driver rockchip_pcie_driver = {
 		.name	= "rockchip-dw-pcie",
 		.of_match_table = rockchip_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = rockchip_pcie_probe,
 };
-- 
2.44.0



             reply	other threads:[~2024-06-25 15:58 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-25 15:57 Anand Moon [this message]
2024-08-07  4:39 ` [PATCH linu-next v1] PCI: dw-rockchip: Enable async probe by default Anand Moon
2024-08-07 16:31 ` Bjorn Helgaas
2024-08-07 17:00   ` Manivannan Sadhasivam
2024-08-08  3:13     ` Anand Moon

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