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From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v1 8/8] PCI: brcmstb: Enable 7712 SOCs
Date: Fri, 28 Jun 2024 16:54:27 -0400	[thread overview]
Message-ID: <20240628205430.24775-9-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20240628205430.24775-1-james.quinlan@broadcom.com>

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The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 9dab577dc1b4..418525c9d249 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1209,7 +1209,9 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
 		 * atypical and should happen only with older devices.
 		 */
 		clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
-		brcm_extend_rbus_timeout(pcie);
+		/* 7712 does not have this (RGR1) timer */
+		if (pcie->type != BCM7712)
+			brcm_extend_rbus_timeout(pcie);
 
 	} else {
 		/*
@@ -1616,6 +1618,13 @@ static const int pcie_offsets_bmips_7425[] = {
 	[PCIE_INTR2_CPU_BASE] = 0x4300,
 };
 
+static const int pcie_offset_bcm7712[] = {
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x9004,
+	[PCIE_HARD_DEBUG] = 0x4304,
+	[PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
 static const struct pcie_cfg_data generic_cfg = {
 	.offsets	= pcie_offsets,
 	.type		= GENERIC,
@@ -1674,6 +1683,13 @@ static const struct pcie_cfg_data bcm7216_cfg = {
 	.has_phy	= true,
 };
 
+static const struct pcie_cfg_data bcm7712_cfg = {
+	.offsets	= pcie_offset_bcm7712,
+	.perst_set	= brcm_pcie_perst_set_7278,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+	.type		= BCM7712,
+};
+
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
 	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1683,6 +1699,7 @@ static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
 	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
 	{},
 };
 
-- 
2.17.1


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      parent reply	other threads:[~2024-06-28 20:56 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-28 20:54 [PATCH v1 0/8] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-06-28 20:54 ` [PATCH v1 1/8] dt-bindings: PCI: Add Broadcom STB 7712 SOC, update maintainter Jim Quinlan
2024-07-01  9:12   ` Krzysztof Kozlowski
2024-07-02 21:57     ` Jim Quinlan
2024-07-03  4:33       ` Krzysztof Kozlowski
2024-07-01 19:47   ` Bjorn Helgaas
2024-06-28 20:54 ` [PATCH v1 2/8] PCI: brcmstb: Use "clk_out" error path label Jim Quinlan
2024-07-01 19:49   ` Bjorn Helgaas
2024-07-03 18:45   ` [PATCH " Markus Elfring
2024-06-28 20:54 ` [PATCH v1 3/8] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-02 12:59   ` Stanimir Varbanov
2024-07-02 18:36     ` Jim Quinlan
2024-07-03 13:09       ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 4/8] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-01  9:48   ` Philipp Zabel
2024-07-02 13:02   ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 5/8] PCI: brcmstb: Two more register offsets vary by SOC Jim Quinlan
2024-07-01 17:32   ` Bjorn Helgaas
2024-06-28 20:54 ` [PATCH v1 6/8] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-02 13:10   ` Stanimir Varbanov
2024-07-02 17:59     ` Jim Quinlan
2024-07-03 12:38       ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 7/8] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-06-28 20:54 ` Jim Quinlan [this message]

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