From: "Krzysztof Wilczyński" <kw@linux.com>
To: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Siddharth Vadapalli <s-vadapalli@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
Date: Sat, 29 Jun 2024 06:19:58 +0900 [thread overview]
Message-ID: <20240628211958.GA2213719@rocinante> (raw)
In-Reply-To: <16e1fcae-1ea7-46be-b157-096e05661b15@siemens.com>
Hello,
> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
>
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 bytes. Add workaround
> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.
>
> [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf
Jan, thank you for picking up this patch. Siddharth, thank you for being
very thorough, chasing after old review comments to be addressed.
Much appreciated on both accounts!
Krzysztof
next prev parent reply other threads:[~2024-06-28 21:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-28 11:45 [PATCH v5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Jan Kiszka
2024-06-28 21:19 ` Krzysztof Wilczyński [this message]
2024-06-28 22:00 ` Krzysztof Wilczyński
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