From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC8B9C30653 for ; Mon, 1 Jul 2024 13:35:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pfhp05gxKqLcCtelE9T4ksYYTQ/1ZRRtwyxkpY0FkB8=; b=M/xV95L1pP8YWz7UVo+wFRFVD6 MK+kfJB8ATlsQDLKk3oSi6v/yJUh359xe6yeF6tLMIioCfWAAYDSoXMnvCT+hxDh4JVZE7Vfv8Mgm oToP2ZQ/M1QOl+WB75NY36TUUgr1ujcwKqCKVygr6BpKILpZN/K8WXEd1Fud3xNlAjt/rJXTVUH/a Ln9YKh7QrFb59pzi8hUAkHoDG2PqDcvJwHwdU7oN6M+NeHKChTKXQfByXQFDeQRXArRNzWlXzomJj kj4WR5OW4lSMxDp4/1yNc7xEHTqSiPguMc83T83rjCwcq2Id/cWfx8eXkfWuejrIicuPuDmW/1GLs AFOCBtig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOHBr-00000003W8b-1pud; Mon, 01 Jul 2024 13:35:31 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOHBg-00000003W4x-1zVc for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 13:35:21 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 77EA0612FD; Mon, 1 Jul 2024 13:35:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F3E1C116B1; Mon, 1 Jul 2024 13:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719840919; bh=452Q4FhZJ0mADWWLmyzoJKxOQya9ASi8Mich7VuTw24=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=obfwfaXZJuo7CKWqimApdmuV6R+GIeO9qj255mFWzzCb/bf29xrbGB0kNUz8ziT7r xLQ4ZK3JLomhHJTwIM0LIndI2ftjImn5aTlEzNj8NawFcqSVDlZrGkTHXjnRkA1Sf8 TDLXP23gqmKaBatLMfyuzTxdSLo9y3n9imHVSmzBSgeKO25JZ1MeWa7C23V2n8I1H0 6CfzYRDFefZORpoLqkh1DDLtGYjiDxoD0QnGSJl3PGQ2qVMmDzad6kMxIAYV8a6Xpf kEsAOr07kgfEnroGDkS+kKej+ye0fzWjW3Axp57ZfMZV8YchAgVfXFlu+qW4ClPTnT fA2wv5x4hOclg== Date: Mon, 1 Jul 2024 14:35:14 +0100 From: Will Deacon To: Robin Murphy Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, jialong.yang@shingroup.cn Subject: Re: [PATCH 2/3] perf: Add driver for Arm NI-700 interconnect PMU Message-ID: <20240701133514.GB2250@willie-the-truck> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_063520_737498_0CFC9EAE X-CRM114-Status: GOOD ( 32.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 25, 2024 at 01:29:53PM +0100, Robin Murphy wrote: > The Arm NI-700 Network-on-Chip Interconnect has a relatively > straightforward design with a hierarchy of voltage, power, and clock > domains, where each clock domain then contains a number of interface > units and a PMU which can monitor events thereon. As such, it begets a > relatively straightforward driver to interface those PMUs with perf. > > Even more so than with arm-cmn, users will require detailed knowledge of > the wider system topology in order to meaningfully analyse anything, > since the interconnect itself cannot know what lies beyond the boundary > of each inscrutably-numbered interface. Given that, for now they are > also expected to refer to the NI-700 documentation for the relevant > event IDs to provide as well. An identifier is implemented so we can > come back and add jevents if anyone really wants to. > > Signed-off-by: Robin Murphy > --- > drivers/perf/Kconfig | 7 + > drivers/perf/Makefile | 1 + > drivers/perf/arm-ni.c | 767 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 775 insertions(+) > create mode 100644 drivers/perf/arm-ni.c Please can you add some documentation? > +struct arm_ni { > + struct device *dev; > + void __iomem *base; > + enum ni_part part; > + int id; > + int num_cds; > + struct arm_ni_cd cds[]; > +}; Can you use that fancy new __counted_by thing here? > + > +#define cd_to_ni(cd) container_of((cd), struct arm_ni, cds[(cd)->id]) > +#define pmu_to_cd(p) container_of((p), struct arm_ni_cd, pmu) > + > +#define cd_for_each_unit(cd, u) \ > + for (struct arm_ni_unit *u = cd->units; u < cd->units + cd->num_units; u++) > + > +static int arm_ni_hp_state; > + > +struct arm_ni_event_attr { > + struct device_attribute attr; > + enum ni_node_type type; > +}; > + > +#define NI_EVENT_ATTR(_name, _type) \ > + (&((struct arm_ni_event_attr[]) {{ \ > + .attr = __ATTR(_name, 0444, arm_ni_event_show, NULL), \ > + .type = _type, \ > + }})[0].attr.attr) > + > +static ssize_t arm_ni_event_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct arm_ni_event_attr *eattr = container_of(attr, typeof(*eattr), attr); > + > + if (eattr->type == NI_PMU) > + return sysfs_emit(buf, "type=0x%x\n", eattr->type); > + > + return sysfs_emit(buf, "type=0x%x,eventid=?,nodeid=?\n", eattr->type); I'm struggling to see what this is doing. Please can you explain it a bit? For example, does the perf tool parse those "=?" entries, and why is it useful to print out only the NI_PMU value for the other events? > +} > + > +static umode_t arm_ni_event_attr_is_visible(struct kobject *kobj, > + struct attribute *attr, int unused) > +{ > + struct device *dev = kobj_to_dev(kobj); > + struct arm_ni_cd *cd = pmu_to_cd(dev_get_drvdata(dev)); > + struct arm_ni_event_attr *eattr; > + > + eattr = container_of(attr, typeof(*eattr), attr.attr); > + > + cd_for_each_unit(cd, unit) { > + if (unit->type == eattr->type && unit->ns) > + return attr->mode; > + } > + > + return 0; > +} > + > +static struct attribute *arm_ni_event_attrs[] = { > + NI_EVENT_ATTR(asni, NI_ASNI), > + NI_EVENT_ATTR(amni, NI_AMNI), > + NI_EVENT_ATTR(cycles, NI_PMU), > + NI_EVENT_ATTR(hsni, NI_HSNI), > + NI_EVENT_ATTR(hmni, NI_HMNI), > + NI_EVENT_ATTR(pmni, NI_PMNI), > + NULL > +}; [...] > +static bool arm_ni_validate_event(struct perf_event *this, > + struct perf_event *that, int *count) > +{ > + if (is_software_event(this)) > + return true; > + if (this->pmu != that->pmu) > + return false; > + return --count[NI_EVENT_TYPE(this) == NI_PMU] >= 0; This is pretty horrible to read :/ I don't know the details of this PMU, so is the count array saying that you can have NI_NUM_COUNTERS events with the NI_PMU type, but only one event of any other type? > +} > + > +static int arm_ni_validate_group(struct perf_event *event) > +{ > + struct perf_event *sibling, *leader; > + int count[2] = {NI_NUM_COUNTERS, 1}; > + > + arm_ni_validate_event(event, event, count); > + > + leader = event->group_leader; > + if (leader != event && !arm_ni_validate_event(leader, event, count)) > + return - EINVAL; > + > + for_each_sibling_event(sibling, leader) { > + if (!arm_ni_validate_event(sibling, event, count)) > + return - EINVAL; > + } > + return 0; > +} > + > +static int arm_ni_event_init(struct perf_event *event) > +{ > + struct arm_ni_cd *cd = pmu_to_cd(event->pmu); > + > + if (event->attr.type != event->pmu->type) > + return -ENOENT; > + > + if (is_sampling_event(event)) > + return -EINVAL; > + > + event->cpu = cd->cpu; > + if (NI_EVENT_TYPE(event) == NI_PMU) > + return arm_ni_validate_group(event); > + > + cd_for_each_unit(cd, unit) { > + if (unit->type == NI_EVENT_TYPE(event) && > + unit->id == NI_EVENT_NODEID(event) && unit->ns) { > + event->hw.config_base = (unsigned long)unit; > + return arm_ni_validate_group(event); > + } > + } > + return -EINVAL; > +} > + > +static u64 arm_ni_read_ccnt(struct arm_ni_cd *cd) > +{ > + u64 l, u_old, u_new; > + > + u_new = readl_relaxed(cd->pmu_base + NI_PMCCNTR_U); > + do { > + u_old = u_new; > + l = readl_relaxed(cd->pmu_base + NI_PMCCNTR_L); > + u_new = readl_relaxed(cd->pmu_base + NI_PMCCNTR_U); > + } while (u_new != u_old); > + > + return (u_new << 32) | l; > +} oh man, they really don't have 64-bit registers on this thing? If we have to loop like this, can we add a timeout just in case the hardware goes wonky? It's like mixing together the worst parts of iopoll.h and io-64-nonatomic-lo-hi.h. There are a few other PMU drivers that look like they could share that code if you added it as a generic helper. Will