* [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields
2024-07-01 16:20 [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Rob Clark
@ 2024-07-01 16:20 ` Rob Clark
2024-07-01 19:13 ` Pranjal Shrivastava
2024-07-01 16:20 ` [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults Rob Clark
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Rob Clark @ 2024-07-01 16:20 UTC (permalink / raw)
To: iommu
Cc: linux-arm-msm, Stephen Boyd, Robin Murphy, Pranjal Shrivastava,
Rob Clark, Thierry Reding, Krishna Reddy, Will Deacon,
Joerg Roedel, Rob Clark, Jason Gunthorpe, Jerry Snitselaar,
Krzysztof Kozlowski, Georgi Djakov, Dmitry Baryshkov,
open list:TEGRA IOMMU DRIVERS, moderated list:ARM SMMU DRIVERS,
open list
From: Rob Clark <robdclark@chromium.org>
For consistency, add the "CB" prefix to the bitfield defines for context
registers.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 2 +-
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 18 +++----
drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +--
drivers/iommu/arm/arm-smmu/arm-smmu.h | 50 +++++++++----------
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 4 +-
5 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
index 957d988b6d83..4b2994b6126d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
@@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_FSR_FAULT))
+ if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
return IRQ_NONE;
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 552199cbd9e2..e4ee78fb6a66 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) {
+ if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) {
u32 sctlr_orig, sctlr;
/*
@@ -298,7 +298,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (fsr & ARM_SMMU_FSR_FAULT) {
+ if (fsr & ARM_SMMU_CB_FSR_FAULT) {
/* Clear pending interrupts */
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
@@ -306,7 +306,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
* TBU halt takes care of resuming any stalled transcation.
* Kept it here for completeness sake.
*/
- if (fsr & ARM_SMMU_FSR_SS)
+ if (fsr & ARM_SMMU_CB_FSR_SS)
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
ARM_SMMU_RESUME_TERMINATE);
}
@@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (fsr & ARM_SMMU_FSR_FAULT) {
+ if (fsr & ARM_SMMU_CB_FSR_FAULT) {
/* Clear pending interrupts */
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
- if (fsr & ARM_SMMU_FSR_SS)
+ if (fsr & ARM_SMMU_CB_FSR_SS)
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
ARM_SMMU_RESUME_TERMINATE);
}
@@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
DEFAULT_RATELIMIT_BURST);
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_FSR_FAULT))
+ if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
return IRQ_NONE;
fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
@@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
if (list_empty(&tbu_list)) {
ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (ret == -ENOSYS)
dev_err_ratelimited(smmu->dev,
@@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
phys_soft = ops->iova_to_phys(ops, iova);
tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (!tmp || tmp == -EBUSY) {
dev_dbg(smmu->dev,
"Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
@@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
/* Retry or terminate any stalled transactions */
- if (fsr & ARM_SMMU_FSR_SS)
+ if (fsr & ARM_SMMU_CB_FSR_SS)
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 87c81f75cf84..23cf91ac409b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -415,7 +415,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
int ret;
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_FSR_FAULT))
+ if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
return IRQ_NONE;
fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
@@ -423,7 +423,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (ret == -ENOSYS)
dev_err_ratelimited(smmu->dev,
@@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR;
- if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE),
+ if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE),
5, 50)) {
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
dev_err(dev,
@@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
/* Make sure all context banks are disabled and clear CB_FSR */
for (i = 0; i < smmu->num_context_banks; ++i) {
arm_smmu_write_context_bank(smmu, i);
- arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+ arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
}
/* Invalidate the TLB, just in case */
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 4765c6945c34..b04a00126a12 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -196,34 +196,34 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_PAR_F BIT(0)
#define ARM_SMMU_CB_FSR 0x58
-#define ARM_SMMU_FSR_MULTI BIT(31)
-#define ARM_SMMU_FSR_SS BIT(30)
-#define ARM_SMMU_FSR_UUT BIT(8)
-#define ARM_SMMU_FSR_ASF BIT(7)
-#define ARM_SMMU_FSR_TLBLKF BIT(6)
-#define ARM_SMMU_FSR_TLBMCF BIT(5)
-#define ARM_SMMU_FSR_EF BIT(4)
-#define ARM_SMMU_FSR_PF BIT(3)
-#define ARM_SMMU_FSR_AFF BIT(2)
-#define ARM_SMMU_FSR_TF BIT(1)
-
-#define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \
- ARM_SMMU_FSR_ASF | \
- ARM_SMMU_FSR_TLBMCF | \
- ARM_SMMU_FSR_TLBLKF)
-
-#define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \
- ARM_SMMU_FSR_SS | \
- ARM_SMMU_FSR_UUT | \
- ARM_SMMU_FSR_EF | \
- ARM_SMMU_FSR_PF | \
- ARM_SMMU_FSR_TF | \
- ARM_SMMU_FSR_IGN)
+#define ARM_SMMU_CB_FSR_MULTI BIT(31)
+#define ARM_SMMU_CB_FSR_SS BIT(30)
+#define ARM_SMMU_CB_FSR_UUT BIT(8)
+#define ARM_SMMU_CB_FSR_ASF BIT(7)
+#define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
+#define ARM_SMMU_CB_FSR_TLBMCF BIT(5)
+#define ARM_SMMU_CB_FSR_EF BIT(4)
+#define ARM_SMMU_CB_FSR_PF BIT(3)
+#define ARM_SMMU_CB_FSR_AFF BIT(2)
+#define ARM_SMMU_CB_FSR_TF BIT(1)
+
+#define ARM_SMMU_CB_FSR_IGN (ARM_SMMU_CB_FSR_AFF | \
+ ARM_SMMU_CB_FSR_ASF | \
+ ARM_SMMU_CB_FSR_TLBMCF | \
+ ARM_SMMU_CB_FSR_TLBLKF)
+
+#define ARM_SMMU_CB_FSR_FAULT (ARM_SMMU_CB_FSR_MULTI | \
+ ARM_SMMU_CB_FSR_SS | \
+ ARM_SMMU_CB_FSR_UUT | \
+ ARM_SMMU_CB_FSR_EF | \
+ ARM_SMMU_CB_FSR_PF | \
+ ARM_SMMU_CB_FSR_TF | \
+ ARM_SMMU_CB_FSR_IGN)
#define ARM_SMMU_CB_FAR 0x60
#define ARM_SMMU_CB_FSYNR0 0x68
-#define ARM_SMMU_FSYNR0_WNR BIT(4)
+#define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
#define ARM_SMMU_CB_FSYNR1 0x6c
@@ -237,7 +237,7 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_ATS1PR 0x800
#define ARM_SMMU_CB_ATSR 0x8f0
-#define ARM_SMMU_ATSR_ACTIVE BIT(0)
+#define ARM_SMMU_CB_ATSR_ACTIVE BIT(0)
#define ARM_SMMU_RESUME_TERMINATE BIT(0)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index e079bb7a993e..b98a7a598b89 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_FSR_FAULT))
+ if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
return IRQ_NONE;
fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
@@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
/* Clear context bank fault address fault status registers */
iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
- iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
/* TTBRs */
iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields
2024-07-01 16:20 ` [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields Rob Clark
@ 2024-07-01 19:13 ` Pranjal Shrivastava
0 siblings, 0 replies; 12+ messages in thread
From: Pranjal Shrivastava @ 2024-07-01 19:13 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, linux-arm-msm, Stephen Boyd, Robin Murphy, Rob Clark,
Thierry Reding, Krishna Reddy, Will Deacon, Joerg Roedel,
Jason Gunthorpe, Jerry Snitselaar, Krzysztof Kozlowski,
Georgi Djakov, Dmitry Baryshkov, open list:TEGRA IOMMU DRIVERS,
moderated list:ARM SMMU DRIVERS, open list
On Mon, Jul 1, 2024 at 9:50 PM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> For consistency, add the "CB" prefix to the bitfield defines for context
> registers.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 2 +-
> .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 18 +++----
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +--
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 50 +++++++++----------
> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 4 +-
> 5 files changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> index 957d988b6d83..4b2994b6126d 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> @@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
>
> fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_FSR_FAULT))
> + if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> return IRQ_NONE;
>
> fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> index 552199cbd9e2..e4ee78fb6a66 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> @@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma
> writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
>
> fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) {
> + if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) {
> u32 sctlr_orig, sctlr;
>
> /*
> @@ -298,7 +298,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
>
> fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (fsr & ARM_SMMU_FSR_FAULT) {
> + if (fsr & ARM_SMMU_CB_FSR_FAULT) {
> /* Clear pending interrupts */
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
> @@ -306,7 +306,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
> * TBU halt takes care of resuming any stalled transcation.
> * Kept it here for completeness sake.
> */
> - if (fsr & ARM_SMMU_FSR_SS)
> + if (fsr & ARM_SMMU_CB_FSR_SS)
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
> ARM_SMMU_RESUME_TERMINATE);
> }
> @@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
> phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
>
> fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (fsr & ARM_SMMU_FSR_FAULT) {
> + if (fsr & ARM_SMMU_CB_FSR_FAULT) {
> /* Clear pending interrupts */
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
> - if (fsr & ARM_SMMU_FSR_SS)
> + if (fsr & ARM_SMMU_CB_FSR_SS)
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
> ARM_SMMU_RESUME_TERMINATE);
> }
> @@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> DEFAULT_RATELIMIT_BURST);
>
> fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_FSR_FAULT))
> + if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> return IRQ_NONE;
>
> fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> @@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
>
> if (list_empty(&tbu_list)) {
> ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> if (ret == -ENOSYS)
> dev_err_ratelimited(smmu->dev,
> @@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> phys_soft = ops->iova_to_phys(ops, iova);
>
> tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> if (!tmp || tmp == -EBUSY) {
> dev_dbg(smmu->dev,
> "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
> @@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
>
> /* Retry or terminate any stalled transactions */
> - if (fsr & ARM_SMMU_FSR_SS)
> + if (fsr & ARM_SMMU_CB_FSR_SS)
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
> }
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index 87c81f75cf84..23cf91ac409b 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -415,7 +415,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> int ret;
>
> fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_FSR_FAULT))
> + if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> return IRQ_NONE;
>
> fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> @@ -423,7 +423,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
>
> ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> if (ret == -ENOSYS)
> dev_err_ratelimited(smmu->dev,
> @@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
>
> reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR;
> - if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE),
> + if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE),
> 5, 50)) {
> spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
> dev_err(dev,
> @@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
> /* Make sure all context banks are disabled and clear CB_FSR */
> for (i = 0; i < smmu->num_context_banks; ++i) {
> arm_smmu_write_context_bank(smmu, i);
> - arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
> }
>
> /* Invalidate the TLB, just in case */
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index 4765c6945c34..b04a00126a12 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -196,34 +196,34 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_PAR_F BIT(0)
>
> #define ARM_SMMU_CB_FSR 0x58
> -#define ARM_SMMU_FSR_MULTI BIT(31)
> -#define ARM_SMMU_FSR_SS BIT(30)
> -#define ARM_SMMU_FSR_UUT BIT(8)
> -#define ARM_SMMU_FSR_ASF BIT(7)
> -#define ARM_SMMU_FSR_TLBLKF BIT(6)
> -#define ARM_SMMU_FSR_TLBMCF BIT(5)
> -#define ARM_SMMU_FSR_EF BIT(4)
> -#define ARM_SMMU_FSR_PF BIT(3)
> -#define ARM_SMMU_FSR_AFF BIT(2)
> -#define ARM_SMMU_FSR_TF BIT(1)
> -
> -#define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \
> - ARM_SMMU_FSR_ASF | \
> - ARM_SMMU_FSR_TLBMCF | \
> - ARM_SMMU_FSR_TLBLKF)
> -
> -#define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \
> - ARM_SMMU_FSR_SS | \
> - ARM_SMMU_FSR_UUT | \
> - ARM_SMMU_FSR_EF | \
> - ARM_SMMU_FSR_PF | \
> - ARM_SMMU_FSR_TF | \
> - ARM_SMMU_FSR_IGN)
> +#define ARM_SMMU_CB_FSR_MULTI BIT(31)
> +#define ARM_SMMU_CB_FSR_SS BIT(30)
> +#define ARM_SMMU_CB_FSR_UUT BIT(8)
> +#define ARM_SMMU_CB_FSR_ASF BIT(7)
> +#define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
> +#define ARM_SMMU_CB_FSR_TLBMCF BIT(5)
> +#define ARM_SMMU_CB_FSR_EF BIT(4)
> +#define ARM_SMMU_CB_FSR_PF BIT(3)
> +#define ARM_SMMU_CB_FSR_AFF BIT(2)
> +#define ARM_SMMU_CB_FSR_TF BIT(1)
> +
> +#define ARM_SMMU_CB_FSR_IGN (ARM_SMMU_CB_FSR_AFF | \
> + ARM_SMMU_CB_FSR_ASF | \
> + ARM_SMMU_CB_FSR_TLBMCF | \
> + ARM_SMMU_CB_FSR_TLBLKF)
> +
> +#define ARM_SMMU_CB_FSR_FAULT (ARM_SMMU_CB_FSR_MULTI | \
> + ARM_SMMU_CB_FSR_SS | \
> + ARM_SMMU_CB_FSR_UUT | \
> + ARM_SMMU_CB_FSR_EF | \
> + ARM_SMMU_CB_FSR_PF | \
> + ARM_SMMU_CB_FSR_TF | \
> + ARM_SMMU_CB_FSR_IGN)
>
> #define ARM_SMMU_CB_FAR 0x60
>
> #define ARM_SMMU_CB_FSYNR0 0x68
> -#define ARM_SMMU_FSYNR0_WNR BIT(4)
> +#define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
>
> #define ARM_SMMU_CB_FSYNR1 0x6c
>
> @@ -237,7 +237,7 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_ATS1PR 0x800
>
> #define ARM_SMMU_CB_ATSR 0x8f0
> -#define ARM_SMMU_ATSR_ACTIVE BIT(0)
> +#define ARM_SMMU_CB_ATSR_ACTIVE BIT(0)
>
> #define ARM_SMMU_RESUME_TERMINATE BIT(0)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index e079bb7a993e..b98a7a598b89 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
>
> fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
>
> - if (!(fsr & ARM_SMMU_FSR_FAULT))
> + if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> return IRQ_NONE;
>
> fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
> @@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
>
> /* Clear context bank fault address fault status registers */
> iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
> - iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
>
> /* TTBRs */
> iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
> --
> 2.45.2
>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults
2024-07-01 16:20 [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Rob Clark
2024-07-01 16:20 ` [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields Rob Clark
@ 2024-07-01 16:20 ` Rob Clark
2024-07-01 19:33 ` Pranjal Shrivastava
2024-07-01 16:20 ` [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Rob Clark
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Rob Clark @ 2024-07-01 16:20 UTC (permalink / raw)
To: iommu
Cc: linux-arm-msm, Stephen Boyd, Robin Murphy, Pranjal Shrivastava,
Rob Clark, Rob Clark, Will Deacon, Joerg Roedel,
moderated list:ARM SMMU DRIVERS, open list
From: Rob Clark <robdclark@chromium.org>
Handled faults can be "normal", don't spam dmesg about them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index e4ee78fb6a66..681fbdfc325d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -419,10 +419,6 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (!tmp || tmp == -EBUSY) {
- dev_dbg(smmu->dev,
- "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
- iova, fsr, fsynr, idx);
- dev_dbg(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft);
ret = IRQ_HANDLED;
resume = ARM_SMMU_RESUME_TERMINATE;
} else {
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults
2024-07-01 16:20 ` [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults Rob Clark
@ 2024-07-01 19:33 ` Pranjal Shrivastava
0 siblings, 0 replies; 12+ messages in thread
From: Pranjal Shrivastava @ 2024-07-01 19:33 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, linux-arm-msm, Stephen Boyd, Robin Murphy, Rob Clark,
Will Deacon, Joerg Roedel, moderated list:ARM SMMU DRIVERS,
open list
On Mon, Jul 1, 2024 at 9:50 PM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Handled faults can be "normal", don't spam dmesg about them.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> index e4ee78fb6a66..681fbdfc325d 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> @@ -419,10 +419,6 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> if (!tmp || tmp == -EBUSY) {
> - dev_dbg(smmu->dev,
> - "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
> - iova, fsr, fsynr, idx);
> - dev_dbg(smmu->dev, "soft iova-to-phys=%pa\n", &phys_soft);
> ret = IRQ_HANDLED;
> resume = ARM_SMMU_RESUME_TERMINATE;
> } else {
> --
> 2.45.2
>
Seems consistent with the arm_smmu_context_fault handler.
Reviewed-by: Pranjal Shrivastava <praan@google.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs
2024-07-01 16:20 [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Rob Clark
2024-07-01 16:20 ` [PATCH v3 1/3] iommu/arm-smmu: Add CB prefix to register bitfields Rob Clark
2024-07-01 16:20 ` [PATCH v3 2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults Rob Clark
@ 2024-07-01 16:20 ` Rob Clark
2024-07-01 19:44 ` Pranjal Shrivastava
2024-08-22 10:09 ` Manivannan Sadhasivam
2024-07-01 20:07 ` [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Pranjal Shrivastava
2024-07-02 18:44 ` Will Deacon
4 siblings, 2 replies; 12+ messages in thread
From: Rob Clark @ 2024-07-01 16:20 UTC (permalink / raw)
To: iommu
Cc: linux-arm-msm, Stephen Boyd, Robin Murphy, Pranjal Shrivastava,
Rob Clark, Rob Clark, Will Deacon, Joerg Roedel, Jason Gunthorpe,
Jerry Snitselaar, Rob Herring, Krzysztof Kozlowski, Georgi Djakov,
Dmitry Baryshkov, moderated list:ARM SMMU DRIVERS, open list
From: Rob Clark <robdclark@chromium.org>
Parse out the bitfields for easier-to-read fault messages.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++---------
drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++----
drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++
3 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 681fbdfc325d..ef93f825f11f 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -383,64 +383,44 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
struct arm_smmu_domain *smmu_domain = dev;
struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
struct arm_smmu_device *smmu = smmu_domain->smmu;
- u32 fsr, fsynr, cbfrsynra, resume = 0;
+ struct arm_smmu_context_fault_info cfi;
+ u32 resume = 0;
int idx = smmu_domain->cfg.cbndx;
phys_addr_t phys_soft;
- unsigned long iova;
int ret, tmp;
static DEFINE_RATELIMIT_STATE(_rs,
DEFAULT_RATELIMIT_INTERVAL,
DEFAULT_RATELIMIT_BURST);
- fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
- return IRQ_NONE;
+ arm_smmu_read_context_fault_info(smmu, idx, &cfi);
- fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
- iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
- cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
+ if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
+ return IRQ_NONE;
if (list_empty(&tbu_list)) {
- ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
+ cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (ret == -ENOSYS)
- dev_err_ratelimited(smmu->dev,
- "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
- fsr, iova, fsynr, cbfrsynra, idx);
+ arm_smmu_print_context_fault_info(smmu, idx, &cfi);
- arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
+ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
return IRQ_HANDLED;
}
- phys_soft = ops->iova_to_phys(ops, iova);
+ phys_soft = ops->iova_to_phys(ops, cfi.iova);
- tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ tmp = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
+ cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
if (!tmp || tmp == -EBUSY) {
ret = IRQ_HANDLED;
resume = ARM_SMMU_RESUME_TERMINATE;
} else {
- phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, iova, fsr);
+ phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr);
if (__ratelimit(&_rs)) {
- dev_err(smmu->dev,
- "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
- fsr, iova, fsynr, cbfrsynra, idx);
- dev_err(smmu->dev,
- "FSR = %08x [%s%s%s%s%s%s%s%s%s], SID=0x%x\n",
- fsr,
- (fsr & 0x02) ? "TF " : "",
- (fsr & 0x04) ? "AFF " : "",
- (fsr & 0x08) ? "PF " : "",
- (fsr & 0x10) ? "EF " : "",
- (fsr & 0x20) ? "TLBMCF " : "",
- (fsr & 0x40) ? "TLBLKF " : "",
- (fsr & 0x80) ? "MHF " : "",
- (fsr & 0x40000000) ? "SS " : "",
- (fsr & 0x80000000) ? "MULTI " : "",
- cbfrsynra);
+ arm_smmu_print_context_fault_info(smmu, idx, &cfi);
dev_err(smmu->dev,
"soft iova-to-phys=%pa\n", &phys_soft);
@@ -474,10 +454,10 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
*/
if (tmp != -EBUSY) {
/* Clear the faulting FSR */
- arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
+ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
/* Retry or terminate any stalled transactions */
- if (fsr & ARM_SMMU_CB_FSR_SS)
+ if (cfi.fsr & ARM_SMMU_CB_FSR_SS)
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 23cf91ac409b..79ec911ae151 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
.tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
};
+
+void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
+ struct arm_smmu_context_fault_info *cfi)
+{
+ cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
+ cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
+ cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
+ cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
+}
+
+void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
+ const struct arm_smmu_context_fault_info *cfi)
+{
+ dev_dbg(smmu->dev,
+ "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
+ cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
+
+ dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",
+ cfi->fsr,
+ (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "",
+ (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),
+ (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "",
+ (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "",
+ cfi->cbfrsynra);
+
+ dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",
+ cfi->fsynr,
+ (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",
+ (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",
+ (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));
+}
+
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
{
- u32 fsr, fsynr, cbfrsynra;
- unsigned long iova;
+ struct arm_smmu_context_fault_info cfi;
struct arm_smmu_domain *smmu_domain = dev;
struct arm_smmu_device *smmu = smmu_domain->smmu;
+ static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
+ DEFAULT_RATELIMIT_BURST);
int idx = smmu_domain->cfg.cbndx;
int ret;
- fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
- if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
- return IRQ_NONE;
+ arm_smmu_read_context_fault_info(smmu, idx, &cfi);
- fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
- iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
- cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
+ if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
+ return IRQ_NONE;
- ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
- fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+ ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
+ cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
- if (ret == -ENOSYS)
- dev_err_ratelimited(smmu->dev,
- "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
- fsr, iova, fsynr, cbfrsynra, idx);
+ if (ret == -ENOSYS && __ratelimit(&rs))
+ arm_smmu_print_context_fault_info(smmu, idx, &cfi);
- arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
+ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
return IRQ_HANDLED;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index b04a00126a12..e2aeb511ae90 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -198,6 +198,7 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_FSR 0x58
#define ARM_SMMU_CB_FSR_MULTI BIT(31)
#define ARM_SMMU_CB_FSR_SS BIT(30)
+#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)
#define ARM_SMMU_CB_FSR_UUT BIT(8)
#define ARM_SMMU_CB_FSR_ASF BIT(7)
#define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
@@ -223,7 +224,14 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_FAR 0x60
#define ARM_SMMU_CB_FSYNR0 0x68
+#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)
#define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
+#define ARM_SMMU_CB_FSYNR0_PNU BIT(5)
+#define ARM_SMMU_CB_FSYNR0_IND BIT(6)
+#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8)
+#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10)
+#define ARM_SMMU_CB_FSYNR0_AFR BIT(11)
+#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)
#define ARM_SMMU_CB_FSYNR1 0x6c
@@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
int arm_mmu500_reset(struct arm_smmu_device *smmu);
+struct arm_smmu_context_fault_info {
+ unsigned long iova;
+ u32 fsr;
+ u32 fsynr;
+ u32 cbfrsynra;
+};
+
+void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
+ struct arm_smmu_context_fault_info *cfi);
+
+void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
+ const struct arm_smmu_context_fault_info *cfi);
+
#endif /* _ARM_SMMU_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs
2024-07-01 16:20 ` [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Rob Clark
@ 2024-07-01 19:44 ` Pranjal Shrivastava
2024-08-22 10:09 ` Manivannan Sadhasivam
1 sibling, 0 replies; 12+ messages in thread
From: Pranjal Shrivastava @ 2024-07-01 19:44 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, linux-arm-msm, Stephen Boyd, Robin Murphy, Rob Clark,
Will Deacon, Joerg Roedel, Jason Gunthorpe, Jerry Snitselaar,
Rob Herring, Krzysztof Kozlowski, Georgi Djakov, Dmitry Baryshkov,
moderated list:ARM SMMU DRIVERS, open list
On Mon, Jul 1, 2024 at 9:50 PM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Parse out the bitfields for easier-to-read fault messages.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++---------
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++----
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++
> 3 files changed, 92 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> index 681fbdfc325d..ef93f825f11f 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
> @@ -383,64 +383,44 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> struct arm_smmu_domain *smmu_domain = dev;
> struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
> struct arm_smmu_device *smmu = smmu_domain->smmu;
> - u32 fsr, fsynr, cbfrsynra, resume = 0;
> + struct arm_smmu_context_fault_info cfi;
> + u32 resume = 0;
> int idx = smmu_domain->cfg.cbndx;
> phys_addr_t phys_soft;
> - unsigned long iova;
> int ret, tmp;
>
> static DEFINE_RATELIMIT_STATE(_rs,
> DEFAULT_RATELIMIT_INTERVAL,
> DEFAULT_RATELIMIT_BURST);
>
> - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> - return IRQ_NONE;
> + arm_smmu_read_context_fault_info(smmu, idx, &cfi);
>
> - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
> + return IRQ_NONE;
>
> if (list_empty(&tbu_list)) {
> - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
> + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> if (ret == -ENOSYS)
> - dev_err_ratelimited(smmu->dev,
> - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> - fsr, iova, fsynr, cbfrsynra, idx);
> + arm_smmu_print_context_fault_info(smmu, idx, &cfi);
>
> - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
> + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
> return IRQ_HANDLED;
> }
>
> - phys_soft = ops->iova_to_phys(ops, iova);
> + phys_soft = ops->iova_to_phys(ops, cfi.iova);
>
> - tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + tmp = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
> + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> if (!tmp || tmp == -EBUSY) {
> ret = IRQ_HANDLED;
> resume = ARM_SMMU_RESUME_TERMINATE;
> } else {
> - phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, iova, fsr);
> + phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr);
>
> if (__ratelimit(&_rs)) {
> - dev_err(smmu->dev,
> - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> - fsr, iova, fsynr, cbfrsynra, idx);
> - dev_err(smmu->dev,
> - "FSR = %08x [%s%s%s%s%s%s%s%s%s], SID=0x%x\n",
> - fsr,
> - (fsr & 0x02) ? "TF " : "",
> - (fsr & 0x04) ? "AFF " : "",
> - (fsr & 0x08) ? "PF " : "",
> - (fsr & 0x10) ? "EF " : "",
> - (fsr & 0x20) ? "TLBMCF " : "",
> - (fsr & 0x40) ? "TLBLKF " : "",
> - (fsr & 0x80) ? "MHF " : "",
> - (fsr & 0x40000000) ? "SS " : "",
> - (fsr & 0x80000000) ? "MULTI " : "",
> - cbfrsynra);
> + arm_smmu_print_context_fault_info(smmu, idx, &cfi);
>
> dev_err(smmu->dev,
> "soft iova-to-phys=%pa\n", &phys_soft);
> @@ -474,10 +454,10 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
> */
> if (tmp != -EBUSY) {
> /* Clear the faulting FSR */
> - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
> + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
>
> /* Retry or terminate any stalled transactions */
> - if (fsr & ARM_SMMU_CB_FSR_SS)
> + if (cfi.fsr & ARM_SMMU_CB_FSR_SS)
> arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
> }
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index 23cf91ac409b..79ec911ae151 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
> .tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
> };
>
> +
> +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + struct arm_smmu_context_fault_info *cfi)
> +{
> + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> +}
> +
> +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + const struct arm_smmu_context_fault_info *cfi)
> +{
> + dev_dbg(smmu->dev,
> + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
> +
> + dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",
> + cfi->fsr,
> + (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "",
> + (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),
> + (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "",
> + cfi->cbfrsynra);
> +
> + dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",
> + cfi->fsynr,
> + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",
> + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));
> +}
> +
> static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> {
> - u32 fsr, fsynr, cbfrsynra;
> - unsigned long iova;
> + struct arm_smmu_context_fault_info cfi;
> struct arm_smmu_domain *smmu_domain = dev;
> struct arm_smmu_device *smmu = smmu_domain->smmu;
> + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
> + DEFAULT_RATELIMIT_BURST);
> int idx = smmu_domain->cfg.cbndx;
> int ret;
>
> - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> - return IRQ_NONE;
> + arm_smmu_read_context_fault_info(smmu, idx, &cfi);
>
> - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
> + return IRQ_NONE;
>
> - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
> + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> - if (ret == -ENOSYS)
> - dev_err_ratelimited(smmu->dev,
> - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> - fsr, iova, fsynr, cbfrsynra, idx);
> + if (ret == -ENOSYS && __ratelimit(&rs))
> + arm_smmu_print_context_fault_info(smmu, idx, &cfi);
>
> - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
> + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index b04a00126a12..e2aeb511ae90 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -198,6 +198,7 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_FSR 0x58
> #define ARM_SMMU_CB_FSR_MULTI BIT(31)
> #define ARM_SMMU_CB_FSR_SS BIT(30)
> +#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)
> #define ARM_SMMU_CB_FSR_UUT BIT(8)
> #define ARM_SMMU_CB_FSR_ASF BIT(7)
> #define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
> @@ -223,7 +224,14 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_FAR 0x60
>
> #define ARM_SMMU_CB_FSYNR0 0x68
> +#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)
> #define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
> +#define ARM_SMMU_CB_FSYNR0_PNU BIT(5)
> +#define ARM_SMMU_CB_FSYNR0_IND BIT(6)
> +#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8)
> +#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10)
> +#define ARM_SMMU_CB_FSYNR0_AFR BIT(11)
> +#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)
>
> #define ARM_SMMU_CB_FSYNR1 0x6c
>
> @@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
> void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
> int arm_mmu500_reset(struct arm_smmu_device *smmu);
>
> +struct arm_smmu_context_fault_info {
> + unsigned long iova;
> + u32 fsr;
> + u32 fsynr;
> + u32 cbfrsynra;
> +};
Super Nit: (non-block) Let's define this with the structs above.
Right below struct arm_smmu_master_cfg.
> +
> +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + struct arm_smmu_context_fault_info *cfi);
> +
> +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + const struct arm_smmu_context_fault_info *cfi);
> +
> #endif /* _ARM_SMMU_H */
> --
> 2.45.2
>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs
2024-07-01 16:20 ` [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Rob Clark
2024-07-01 19:44 ` Pranjal Shrivastava
@ 2024-08-22 10:09 ` Manivannan Sadhasivam
2024-08-22 10:31 ` Pranjal Shrivastava
1 sibling, 1 reply; 12+ messages in thread
From: Manivannan Sadhasivam @ 2024-08-22 10:09 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, linux-arm-msm, Stephen Boyd, Robin Murphy,
Pranjal Shrivastava, Rob Clark, Will Deacon, Joerg Roedel,
Jason Gunthorpe, Jerry Snitselaar, Rob Herring,
Krzysztof Kozlowski, Georgi Djakov, Dmitry Baryshkov,
moderated list:ARM SMMU DRIVERS, open list
On Mon, Jul 01, 2024 at 09:20:12AM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Parse out the bitfields for easier-to-read fault messages.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++---------
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++----
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++
> 3 files changed, 92 insertions(+), 51 deletions(-)
>
[...]
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index 23cf91ac409b..79ec911ae151 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
> .tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
> };
>
> +
> +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + struct arm_smmu_context_fault_info *cfi)
> +{
> + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> +}
> +
> +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + const struct arm_smmu_context_fault_info *cfi)
> +{
> + dev_dbg(smmu->dev,
> + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
> +
I just happen to hit an IOMMU fault in 6.11-rc4 and I did not see the 'Unhandled
context fault' log, but just the register dump in dmesg. Tracking that lead me
to this patch.
May I know the reasoning behind making the actual error message _dbg()? It is
intentional first place?
- Mani
> + dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",
> + cfi->fsr,
> + (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "",
> + (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),
> + (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "",
> + (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "",
> + cfi->cbfrsynra);
> +
> + dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",
> + cfi->fsynr,
> + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",
> + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",
> + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));
> +}
> +
> static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> {
> - u32 fsr, fsynr, cbfrsynra;
> - unsigned long iova;
> + struct arm_smmu_context_fault_info cfi;
> struct arm_smmu_domain *smmu_domain = dev;
> struct arm_smmu_device *smmu = smmu_domain->smmu;
> + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
> + DEFAULT_RATELIMIT_BURST);
> int idx = smmu_domain->cfg.cbndx;
> int ret;
>
> - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> - if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> - return IRQ_NONE;
> + arm_smmu_read_context_fault_info(smmu, idx, &cfi);
>
> - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
> + return IRQ_NONE;
>
> - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
> + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
>
> - if (ret == -ENOSYS)
> - dev_err_ratelimited(smmu->dev,
> - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> - fsr, iova, fsynr, cbfrsynra, idx);
> + if (ret == -ENOSYS && __ratelimit(&rs))
> + arm_smmu_print_context_fault_info(smmu, idx, &cfi);
>
> - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
> + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
> return IRQ_HANDLED;
> }
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index b04a00126a12..e2aeb511ae90 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -198,6 +198,7 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_FSR 0x58
> #define ARM_SMMU_CB_FSR_MULTI BIT(31)
> #define ARM_SMMU_CB_FSR_SS BIT(30)
> +#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)
> #define ARM_SMMU_CB_FSR_UUT BIT(8)
> #define ARM_SMMU_CB_FSR_ASF BIT(7)
> #define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
> @@ -223,7 +224,14 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_CB_FAR 0x60
>
> #define ARM_SMMU_CB_FSYNR0 0x68
> +#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)
> #define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
> +#define ARM_SMMU_CB_FSYNR0_PNU BIT(5)
> +#define ARM_SMMU_CB_FSYNR0_IND BIT(6)
> +#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8)
> +#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10)
> +#define ARM_SMMU_CB_FSYNR0_AFR BIT(11)
> +#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)
>
> #define ARM_SMMU_CB_FSYNR1 0x6c
>
> @@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
> void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
> int arm_mmu500_reset(struct arm_smmu_device *smmu);
>
> +struct arm_smmu_context_fault_info {
> + unsigned long iova;
> + u32 fsr;
> + u32 fsynr;
> + u32 cbfrsynra;
> +};
> +
> +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + struct arm_smmu_context_fault_info *cfi);
> +
> +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> + const struct arm_smmu_context_fault_info *cfi);
> +
> #endif /* _ARM_SMMU_H */
> --
> 2.45.2
>
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs
2024-08-22 10:09 ` Manivannan Sadhasivam
@ 2024-08-22 10:31 ` Pranjal Shrivastava
2024-08-22 11:12 ` Manivannan Sadhasivam
0 siblings, 1 reply; 12+ messages in thread
From: Pranjal Shrivastava @ 2024-08-22 10:31 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Rob Clark, iommu, linux-arm-msm, Stephen Boyd, Robin Murphy,
Rob Clark, Will Deacon, Joerg Roedel, Jason Gunthorpe,
Jerry Snitselaar, Rob Herring, Krzysztof Kozlowski, Georgi Djakov,
Dmitry Baryshkov, moderated list:ARM SMMU DRIVERS, open list
On Thu, Aug 22, 2024 at 03:39:41PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Jul 01, 2024 at 09:20:12AM -0700, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Parse out the bitfields for easier-to-read fault messages.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++---------
> > drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++----
> > drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++
> > 3 files changed, 92 insertions(+), 51 deletions(-)
> >
>
> [...]
>
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > index 23cf91ac409b..79ec911ae151 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
> > .tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
> > };
> >
> > +
> > +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > + struct arm_smmu_context_fault_info *cfi)
> > +{
> > + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> > + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> > + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> > + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> > +}
> > +
> > +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > + const struct arm_smmu_context_fault_info *cfi)
> > +{
> > + dev_dbg(smmu->dev,
> > + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> > + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
> > +
>
> I just happen to hit an IOMMU fault in 6.11-rc4 and I did not see the 'Unhandled
> context fault' log, but just the register dump in dmesg. Tracking that lead me
> to this patch.
>
> May I know the reasoning behind making the actual error message _dbg()? It is
> intentional first place?
>
> - Mani
Hi Mani,
That was a miss in this series, but it was fixed recently in [1].
I think it should land soon.
[1] https://lore.kernel.org/linux-iommu/172381862229.1794487.17068761066364130246.b4-ty@kernel.org/
Thanks,
Pranjal
>
> > + dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",
> > + cfi->fsr,
> > + (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "",
> > + (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),
> > + (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "",
> > + (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "",
> > + cfi->cbfrsynra);
> > +
> > + dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",
> > + cfi->fsynr,
> > + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",
> > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",
> > + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));
> > +}
> > +
> > static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> > {
> > - u32 fsr, fsynr, cbfrsynra;
> > - unsigned long iova;
> > + struct arm_smmu_context_fault_info cfi;
> > struct arm_smmu_domain *smmu_domain = dev;
> > struct arm_smmu_device *smmu = smmu_domain->smmu;
> > + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
> > + DEFAULT_RATELIMIT_BURST);
> > int idx = smmu_domain->cfg.cbndx;
> > int ret;
> >
> > - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> > - if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
> > - return IRQ_NONE;
> > + arm_smmu_read_context_fault_info(smmu, idx, &cfi);
> >
> > - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> > - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> > - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> > + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))
> > + return IRQ_NONE;
> >
> > - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
> > - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> > + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,
> > + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
> >
> > - if (ret == -ENOSYS)
> > - dev_err_ratelimited(smmu->dev,
> > - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> > - fsr, iova, fsynr, cbfrsynra, idx);
> > + if (ret == -ENOSYS && __ratelimit(&rs))
> > + arm_smmu_print_context_fault_info(smmu, idx, &cfi);
> >
> > - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
> > + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);
> > return IRQ_HANDLED;
> > }
> >
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> > index b04a00126a12..e2aeb511ae90 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> > @@ -198,6 +198,7 @@ enum arm_smmu_cbar_type {
> > #define ARM_SMMU_CB_FSR 0x58
> > #define ARM_SMMU_CB_FSR_MULTI BIT(31)
> > #define ARM_SMMU_CB_FSR_SS BIT(30)
> > +#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9)
> > #define ARM_SMMU_CB_FSR_UUT BIT(8)
> > #define ARM_SMMU_CB_FSR_ASF BIT(7)
> > #define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
> > @@ -223,7 +224,14 @@ enum arm_smmu_cbar_type {
> > #define ARM_SMMU_CB_FAR 0x60
> >
> > #define ARM_SMMU_CB_FSYNR0 0x68
> > +#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0)
> > #define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
> > +#define ARM_SMMU_CB_FSYNR0_PNU BIT(5)
> > +#define ARM_SMMU_CB_FSYNR0_IND BIT(6)
> > +#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8)
> > +#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10)
> > +#define ARM_SMMU_CB_FSYNR0_AFR BIT(11)
> > +#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16)
> >
> > #define ARM_SMMU_CB_FSYNR1 0x6c
> >
> > @@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
> > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
> > int arm_mmu500_reset(struct arm_smmu_device *smmu);
> >
> > +struct arm_smmu_context_fault_info {
> > + unsigned long iova;
> > + u32 fsr;
> > + u32 fsynr;
> > + u32 cbfrsynra;
> > +};
> > +
> > +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > + struct arm_smmu_context_fault_info *cfi);
> > +
> > +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > + const struct arm_smmu_context_fault_info *cfi);
> > +
> > #endif /* _ARM_SMMU_H */
> > --
> > 2.45.2
> >
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs
2024-08-22 10:31 ` Pranjal Shrivastava
@ 2024-08-22 11:12 ` Manivannan Sadhasivam
0 siblings, 0 replies; 12+ messages in thread
From: Manivannan Sadhasivam @ 2024-08-22 11:12 UTC (permalink / raw)
To: Pranjal Shrivastava
Cc: Rob Clark, iommu, linux-arm-msm, Stephen Boyd, Robin Murphy,
Rob Clark, Will Deacon, Joerg Roedel, Jason Gunthorpe,
Jerry Snitselaar, Rob Herring, Krzysztof Kozlowski, Georgi Djakov,
Dmitry Baryshkov, moderated list:ARM SMMU DRIVERS, open list
On Thu, Aug 22, 2024 at 10:31:45AM +0000, Pranjal Shrivastava wrote:
> On Thu, Aug 22, 2024 at 03:39:41PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Jul 01, 2024 at 09:20:12AM -0700, Rob Clark wrote:
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > Parse out the bitfields for easier-to-read fault messages.
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > > .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++---------
> > > drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++----
> > > drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++
> > > 3 files changed, 92 insertions(+), 51 deletions(-)
> > >
> >
> > [...]
> >
> > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > > index 23cf91ac409b..79ec911ae151 100644
> > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > > @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
> > > .tlb_add_page = arm_smmu_tlb_add_page_s2_v1,
> > > };
> > >
> > > +
> > > +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > > + struct arm_smmu_context_fault_info *cfi)
> > > +{
> > > + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
> > > + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
> > > + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
> > > + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
> > > +}
> > > +
> > > +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,
> > > + const struct arm_smmu_context_fault_info *cfi)
> > > +{
> > > + dev_dbg(smmu->dev,
> > > + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> > > + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);
> > > +
> >
> > I just happen to hit an IOMMU fault in 6.11-rc4 and I did not see the 'Unhandled
> > context fault' log, but just the register dump in dmesg. Tracking that lead me
> > to this patch.
> >
> > May I know the reasoning behind making the actual error message _dbg()? It is
> > intentional first place?
> >
> > - Mani
>
> Hi Mani,
>
> That was a miss in this series, but it was fixed recently in [1].
> I think it should land soon.
>
> [1] https://lore.kernel.org/linux-iommu/172381862229.1794487.17068761066364130246.b4-ty@kernel.org/
>
Cool, thanks!
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages
2024-07-01 16:20 [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Rob Clark
` (2 preceding siblings ...)
2024-07-01 16:20 ` [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Rob Clark
@ 2024-07-01 20:07 ` Pranjal Shrivastava
2024-07-02 18:44 ` Will Deacon
4 siblings, 0 replies; 12+ messages in thread
From: Pranjal Shrivastava @ 2024-07-01 20:07 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, linux-arm-msm, Stephen Boyd, Robin Murphy, Rob Clark,
Dmitry Baryshkov, Georgi Djakov, Jason Gunthorpe,
Jerry Snitselaar, Joerg Roedel, Krishna Reddy,
Krzysztof Kozlowski, moderated list:ARM SMMU DRIVERS, open list,
open list:POWER MANAGEMENT CORE, open list:TEGRA IOMMU DRIVERS,
Rafael J. Wysocki, Rob Herring, Will Deacon
On Mon, Jul 1, 2024 at 9:50 PM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> v3: Split out the reg bitfield renaming, rework
> print_context_fault_info() helper
>
> Rob Clark (3):
> iommu/arm-smmu: Add CB prefix to register bitfields
> iommu/arm-smmu-qcom-debug: Do not print for handled faults
> iommu/arm-smmu: Pretty-print context fault related regs
>
> drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 2 +-
> .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 66 ++++++-----------
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 74 ++++++++++++++-----
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 71 +++++++++++-------
> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 4 +-
> 5 files changed, 127 insertions(+), 90 deletions(-)
>
> --
> 2.45.2
>
For the series:
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Thanks,
Praan
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages
2024-07-01 16:20 [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Rob Clark
` (3 preceding siblings ...)
2024-07-01 20:07 ` [PATCH v3 0/3] iommu/arm-smmu: Prettyify context fault messages Pranjal Shrivastava
@ 2024-07-02 18:44 ` Will Deacon
4 siblings, 0 replies; 12+ messages in thread
From: Will Deacon @ 2024-07-02 18:44 UTC (permalink / raw)
To: iommu, Rob Clark
Cc: catalin.marinas, kernel-team, Will Deacon, linux-arm-msm,
Stephen Boyd, Robin Murphy, Pranjal Shrivastava, Rob Clark,
Dmitry Baryshkov, Georgi Djakov, Jason Gunthorpe,
Jerry Snitselaar, Joerg Roedel, Krishna Reddy,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel, linux-pm,
linux-tegra, Rafael J. Wysocki, Rob Herring
On Mon, 01 Jul 2024 09:20:09 -0700, Rob Clark wrote:
> v3: Split out the reg bitfield renaming, rework
> print_context_fault_info() helper
>
> Rob Clark (3):
> iommu/arm-smmu: Add CB prefix to register bitfields
> iommu/arm-smmu-qcom-debug: Do not print for handled faults
> iommu/arm-smmu: Pretty-print context fault related regs
>
> [...]
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/3] iommu/arm-smmu: Add CB prefix to register bitfields
https://git.kernel.org/will/c/d0166022be37
[2/3] iommu/arm-smmu-qcom-debug: Do not print for handled faults
https://git.kernel.org/will/c/55089781ff77
[3/3] iommu/arm-smmu: Pretty-print context fault related regs
https://git.kernel.org/will/c/d525b0af0c3b
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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