From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BA83C30658 for ; Tue, 2 Jul 2024 17:43:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=x2T7OZTHR7fm69Uac+Ck/29nWJ2Q5x4lRh6+I8fIkd4=; b=x1J4PjEi+IyuCkYd12Hs/CfgCn B1YKg0V6GbgIpgpRILB1ZSMqGaxxM5qNFXpygnTgSYnN/FTZ4IYhJuFdJWcvKCEeecr+bbPCmRtbq eVeWBb54NTkVKArNjJlOtO8n0QiAwd0VWHCKjwYdUCxce7LNqNcUVWPZKwJvnOTC/7K9XlZLc3hhZ XdJKSMyc/eqpVteIu29cAVzd3vXar3PIcSs7zkaBv13Mx2wVnainSzoJjCOUM0safGo2NqmJ9lUt2 G9uh8E9n9kAOR1wLMOQW+pdsh7Nc8el0FPsfOy0SIbxqh0WVVlsia2pwweMQNyujgw26/ps39Frgx MR84jqPQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOhXL-00000007Xi6-3jI5; Tue, 02 Jul 2024 17:43:27 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOhX9-00000007Xey-3Qj9 for linux-arm-kernel@lists.infradead.org; Tue, 02 Jul 2024 17:43:17 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id E689ECE10C9; Tue, 2 Jul 2024 17:43:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E96CC116B1; Tue, 2 Jul 2024 17:43:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719942193; bh=p/qm+v26kUc0ox29i003KD+oPtYq1CDkFNO2ztKMjLg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=CYgbV/GtG/Vpr+Jh7kqIgc+8lKJ/2wgpckkLRxNHBEjVMZUiv5NMujQIOyUqUlpMQ pgGzoHKhD1ouX44P2Ldpzm3nFGkr+uQG989vz3csXrpnUJyXe4Vj/Dqh8TL/bQkSrh 2t0KfLJEmmNtQxMmzhrNJrvjuQAeVjgONEXR4sHQ2oPIZwkXgtyehPRGz4cpAF8zRC LXezH28PZorqTZygHzPE+otjgtjsYvOOqELjTkpkmPDPOBwJC1DC7M9R6/mVLpOdlt ngSyDEg/8bDR9BnKRzNkcTDg9V3GGwiyzFDghLluaCg6yFqEpcG9n3lf8RBEPOti4c sHvWsFivifZuA== Date: Tue, 2 Jul 2024 18:43:07 +0100 From: Will Deacon To: Nicolin Chen Cc: robin.murphy@arm.com, joro@8bytes.org, jgg@nvidia.com, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Message-ID: <20240702174307.GB4740@willie-the-truck> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240702_104316_474716_6747892C X-CRM114-Status: GOOD ( 21.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 12, 2024 at 02:45:31PM -0700, Nicolin Chen wrote: > The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the > CS field of CMD_SYNC. Add a quirk flag to accommodate that. > > Reviewed-by: Jason Gunthorpe > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++++- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index c864c634cd23..ba0e24d5ffbf 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -345,6 +345,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, > FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | > FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); > > + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) { > + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); > + return; > + } > + > if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { > cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); > return; > @@ -690,7 +695,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, > struct arm_smmu_cmdq *cmdq, > struct arm_smmu_ll_queue *llq) > { > - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) > + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && > + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) > return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); > > return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 180c0b1e0658..01227c0de290 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -543,6 +543,9 @@ struct arm_smmu_queue { > > u32 __iomem *prod_reg; > u32 __iomem *cons_reg; > + > +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ > + u32 quirks; Please can you use the existing smmu->options field instead of adding another place to track quirks? Or do you need this only for some of the queues for a given SMMU device? Thanks, Will