[PATCH v3 00/10] armada-370-xp irqchip updates round 2

[PATCH v3 00/10] armada-370-xp irqchip updates round 2

[Marek Behún]

Hi Thomas, Andrew, Ilpo et al.

because, as pointed out by Andrew, reviewing 30 patch series is harder,
I am splitting this "armada-370-xp irqchip updates round 2" series into
smaller parts.

I am sending the first part as v3 of round 2, ten patches only.

After this gets reviewed and merged, I will be sending another 10
patches, and so on.

v1 and v2 at:
  https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=867224
  https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=867511

Marek

Marek Behún (10):
  irqchip/armada-370-xp: Drop _OFFS suffix from some register constants
  irqchip/armada-370-xp: Change register constant suffix from _MSK to
    _MASK
  irqchip/armada-370-xp: Change spaces to tabs
  irqchip/armada-370-xp: Use BIT() and GENMASK() macros
  irqchip/armada-370-xp: Cosmetic fix parentheses in register constant
    definitions
  irqchip/armada-370-xp: Change register constants prefix to MPIC_
  irqchip/armada-370-xp: Use correct type for cpu variable
  irqchip/armada-370-xp: Simplify is_percpu_irq() code
  irqchip/armada-370-xp: Change to SPDX license identifier
  irqchip/armada-370-xp: Declare iterators in for loop

 drivers/irqchip/irq-armada-370-xp.c | 208 ++++++++++++----------------
 1 file changed, 88 insertions(+), 120 deletions(-)

-- 
2.44.2

[PATCH v3 01/10] irqchip/armada-370-xp: Drop _OFFS suffix from some register constants

[Marek Behún]

Some register constants have the _OFFS suffix and some do not. Drop it
to be more consistent.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/irqchip/irq-armada-370-xp.c | 105 +++++++++++++---------------
 1 file changed, 48 insertions(+), 57 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index dce2b80bf439..66d6a2ebc8a5 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -66,15 +66,14 @@
  *                   device
  *
  * The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
- * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
- * to "main_int_base".
+ * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * registers, which are relative to "main_int_base".
  *
  * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK_OFFS and
- * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
- * "per_cpu_int_base". This base address points to a special address,
- * which automatically accesses the registers of the current CPU.
+ * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
+ * registers, which are relative to "per_cpu_int_base". This base
+ * address points to a special address, which automatically accesses
+ * the registers of the current CPU.
  *
  * The per-CPU mask/unmask can also be adjusted using the global
  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
@@ -118,21 +117,21 @@
 
 /* Registers relative to main_int_base */
 #define ARMADA_370_XP_INT_CONTROL		(0x00)
-#define ARMADA_370_XP_SW_TRIG_INT_OFFS		(0x04)
-#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
-#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
+#define ARMADA_370_XP_SW_TRIG_INT		(0x04)
+#define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS	(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS		(0x0c)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
+#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
 #define ARMADA_375_PPI_CAUSE			(0x10)
-#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
-#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
-#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
-#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
+#define ARMADA_370_XP_CPU_INTACK		(0x44)
+#define ARMADA_370_XP_INT_SET_MASK		(0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
+#define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
@@ -220,11 +219,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base +
-				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+		writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base +
-				ARMADA_370_XP_INT_SET_MASK_OFFS);
+		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)
@@ -232,11 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base +
-				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+		writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base +
-				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 #ifdef CONFIG_PCI_MSI
@@ -329,19 +324,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	/* Unmask local doorbell interrupt */
-	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static int armada_370_xp_msi_init(struct device_node *node,
 				  phys_addr_t main_int_phys_base)
 {
-	msi_doorbell_addr = main_int_phys_base +
-		ARMADA_370_XP_SW_TRIG_INT_OFFS;
+	msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
 
 	armada_370_xp_msi_inner_domain =
 		irq_domain_add_linear(NULL, msi_doorbell_size(),
@@ -362,7 +356,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
 
 	/* Unmask low 16 MSI irqs on non-IPI platforms */
 	if (!is_ipi_available())
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
 	return 0;
 }
@@ -391,7 +385,7 @@ static void armada_xp_mpic_perf_init(void)
 
 	/* Enable Performance Counter Overflow interrupts */
 	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
-	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
+	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
 }
 
 #ifdef CONFIG_SMP
@@ -400,17 +394,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
@@ -431,12 +425,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
 	/* submit softirq */
 	writel((map << 8) | d->hwirq, main_int_base +
-		ARMADA_370_XP_SW_TRIG_INT_OFFS);
+		ARMADA_370_XP_SW_TRIG_INT);
 }
 
 static void armada_370_xp_ipi_ack(struct irq_data *d)
 {
-	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 }
 
 static struct irq_chip ipi_irqchip = {
@@ -539,19 +533,19 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
 
 	if (!is_ipi_available())
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	/* Clear pending IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
 	/* Unmask IPI interrupt */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 }
 
 static void armada_xp_mpic_reenable_percpu(void)
@@ -622,9 +616,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 	armada_370_xp_irq_mask(irq_get_irq_data(virq));
 	if (!is_percpu_irq(hw))
 		writel(hw, per_cpu_int_base +
-			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+			ARMADA_370_XP_INT_CLEAR_MASK);
 	else
-		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
 	if (is_percpu_irq(hw)) {
@@ -651,12 +645,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
 	u32 msimask, msinr;
 
-	msimask = readl_relaxed(per_cpu_int_base +
-				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 	msimask &= msi_doorbell_mask();
 
-	writel(~msimask, per_cpu_int_base +
-	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+	writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
 
 	for (msinr = msi_doorbell_start();
 	     msinr < msi_doorbell_end(); msinr++) {
@@ -712,7 +704,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 	do {
 		irqstat = readl_relaxed(per_cpu_int_base +
-					ARMADA_370_XP_CPU_INTACK_OFFS);
+					ARMADA_370_XP_CPU_INTACK);
 		irqnr = irqstat & 0x3FF;
 
 		if (irqnr > 1022)
@@ -735,7 +727,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			int ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
-						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+						ARMADA_370_XP_IN_DRBEL_CAUSE)
 				& IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
@@ -748,8 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base +
-				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 	return 0;
 }
 
@@ -774,13 +765,13 @@ static void armada_370_xp_mpic_resume(void)
 		if (!is_percpu_irq(irq)) {
 			/* Non per-CPU interrupts */
 			writel(irq, per_cpu_int_base +
-			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+			       ARMADA_370_XP_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
 				armada_370_xp_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
 			writel(irq, main_int_base +
-			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+			       ARMADA_370_XP_INT_SET_ENABLE);
 
 			/*
 			 * Re-enable on the current CPU,
@@ -794,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
 
 	/* Reconfigure doorbells for IPIs and MSIs */
 	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
@@ -805,9 +796,9 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	if (src0)
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 	if (src1)
-		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
 
 	if (is_ipi_available())
 		ipi_resume();
@@ -847,7 +838,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =
 		irq_domain_add_linear(node, nr_irqs,
-- 
2.44.2

[PATCH v3 02/10] irqchip/armada-370-xp: Change register constant suffix from _MSK to _MASK

[Marek Behún]

There is one occurrence of suffix _MSK in register constants, others
have _MASK instead. Change the one to _MASK for consistency.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 66d6a2ebc8a5..588a9e2e1887 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -126,7 +126,7 @@
 
 /* Registers relative to per_cpu_int_base */
 #define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
+#define ARMADA_370_XP_IN_DRBEL_MASK		(0x0c)
 #define ARMADA_375_PPI_CAUSE			(0x10)
 #define ARMADA_370_XP_CPU_INTACK		(0x44)
 #define ARMADA_370_XP_INT_SET_MASK		(0x48)
@@ -324,9 +324,9 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	/* Unmask local doorbell interrupt */
 	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
@@ -394,17 +394,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
@@ -539,7 +539,7 @@ static void armada_xp_mpic_smp_cpu_init(void)
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	/* Clear pending IPIs */
 	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
@@ -740,7 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 	return 0;
 }
 
@@ -785,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
 
 	/* Reconfigure doorbells for IPIs and MSIs */
 	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
+	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
-- 
2.44.2

[PATCH v3 03/10] irqchip/armada-370-xp: Change spaces to tabs

[Marek Behún]

Change spaces to tabs in register constants definitions.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 588a9e2e1887..427ba5fd6adc 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -137,13 +137,13 @@
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 /* IPI and MSI interrupt definitions for IPI platforms */
-#define IPI_DOORBELL_START                      (0)
-#define IPI_DOORBELL_END                        (8)
-#define IPI_DOORBELL_MASK                       0xFF
-#define PCI_MSI_DOORBELL_START                  (16)
-#define PCI_MSI_DOORBELL_NR                     (16)
-#define PCI_MSI_DOORBELL_END                    (32)
-#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
+#define IPI_DOORBELL_START			(0)
+#define IPI_DOORBELL_END			(8)
+#define IPI_DOORBELL_MASK			0xFF
+#define PCI_MSI_DOORBELL_START			(16)
+#define PCI_MSI_DOORBELL_NR			(16)
+#define PCI_MSI_DOORBELL_END			(32)
+#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
 
 /* MSI interrupt definitions for non-IPI platforms */
 #define PCI_MSI_FULL_DOORBELL_START		0
-- 
2.44.2

[PATCH v3 04/10] irqchip/armada-370-xp: Use BIT() and GENMASK() macros

[Marek Behún]

Use the BIT() and GENMASK() macros where appropriate.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 427ba5fd6adc..18aca9b5d3b3 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -121,7 +121,7 @@
 #define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
+#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */
@@ -132,18 +132,18 @@
 #define ARMADA_370_XP_INT_SET_MASK		(0x48)
 #define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
 #define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
+#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 /* IPI and MSI interrupt definitions for IPI platforms */
 #define IPI_DOORBELL_START			(0)
 #define IPI_DOORBELL_END			(8)
-#define IPI_DOORBELL_MASK			0xFF
+#define IPI_DOORBELL_MASK			GENMASK(7, 0)
 #define PCI_MSI_DOORBELL_START			(16)
 #define PCI_MSI_DOORBELL_NR			(16)
 #define PCI_MSI_DOORBELL_END			(32)
-#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
+#define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
 
 /* MSI interrupt definitions for non-IPI platforms */
 #define PCI_MSI_FULL_DOORBELL_START		0
@@ -415,7 +415,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
 	/* Convert our logical CPU mask into a physical one. */
 	for_each_cpu(cpu, mask)
-		map |= 1 << cpu_logical_map(cpu);
+		map |= BIT(cpu_logical_map(cpu));
 
 	/*
 	 * Ensure that stores to Normal memory are visible to the
-- 
2.44.2

[PATCH v3 05/10] irqchip/armada-370-xp: Cosmetic fix parentheses in register constant definitions

[Marek Behún]

Drop parentheses where not needed and add where makes sense in register
constant definitions.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 38 ++++++++++++++---------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 18aca9b5d3b3..14d213e9b0d2 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -116,33 +116,33 @@
  */
 
 /* Registers relative to main_int_base */
-#define ARMADA_370_XP_INT_CONTROL		(0x00)
-#define ARMADA_370_XP_SW_TRIG_INT		(0x04)
-#define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
-#define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
-#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
+#define ARMADA_370_XP_INT_CONTROL		0x00
+#define ARMADA_370_XP_SW_TRIG_INT		0x04
+#define ARMADA_370_XP_INT_SET_ENABLE		0x30
+#define ARMADA_370_XP_INT_CLEAR_ENABLE		0x34
+#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + (irq) * 4)
 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
-#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
+#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << (cpuid))
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
-#define ARMADA_370_XP_IN_DRBEL_MASK		(0x0c)
-#define ARMADA_375_PPI_CAUSE			(0x10)
-#define ARMADA_370_XP_CPU_INTACK		(0x44)
-#define ARMADA_370_XP_INT_SET_MASK		(0x48)
-#define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
-#define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE		0x08
+#define ARMADA_370_XP_IN_DRBEL_MASK		0x0c
+#define ARMADA_375_PPI_CAUSE			0x10
+#define ARMADA_370_XP_CPU_INTACK		0x44
+#define ARMADA_370_XP_INT_SET_MASK		0x48
+#define ARMADA_370_XP_INT_CLEAR_MASK		0x4C
+#define ARMADA_370_XP_INT_FABRIC_MASK		0x54
 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
 
-#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
+#define ARMADA_370_XP_MAX_PER_CPU_IRQS		28
 
 /* IPI and MSI interrupt definitions for IPI platforms */
-#define IPI_DOORBELL_START			(0)
-#define IPI_DOORBELL_END			(8)
+#define IPI_DOORBELL_START			0
+#define IPI_DOORBELL_END			8
 #define IPI_DOORBELL_MASK			GENMASK(7, 0)
-#define PCI_MSI_DOORBELL_START			(16)
-#define PCI_MSI_DOORBELL_NR			(16)
-#define PCI_MSI_DOORBELL_END			(32)
+#define PCI_MSI_DOORBELL_START			16
+#define PCI_MSI_DOORBELL_NR			16
+#define PCI_MSI_DOORBELL_END			32
 #define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
 
 /* MSI interrupt definitions for non-IPI platforms */
-- 
2.44.2

[PATCH v3 06/10] irqchip/armada-370-xp: Change register constants prefix to MPIC_

[Marek Behún]

Change the long ARMADA_370_XP_ prefix in register constants (ARMADA_375_
in one case) to MPIC_. The rationale is that it is shorter and more
generic (this controller is called MPIC and is also used on Armada 38x
and 39x).

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 148 +++++++++++++---------------
 1 file changed, 69 insertions(+), 79 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 14d213e9b0d2..8f52de6d8921 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -66,18 +66,17 @@
  *                   device
  *
  * The "global interrupt mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
+ * MPIC_INT_SET_ENABLE and MPIC_INT_CLEAR_ENABLE
  * registers, which are relative to "main_int_base".
  *
- * The "per-CPU mask/unmask" is modified using the
- * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
- * registers, which are relative to "per_cpu_int_base". This base
- * address points to a special address, which automatically accesses
- * the registers of the current CPU.
+ * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK
+ * and MPIC_INT_CLEAR_MASK registers, which are relative to
+ * "per_cpu_int_base". This base address points to a special address,
+ * which automatically accesses the registers of the current CPU.
  *
  * The per-CPU mask/unmask can also be adjusted using the global
- * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
- * to configure interrupt affinity.
+ * per-interrupt MPIC_INT_SOURCE_CTL register, which we use to
+ * configure interrupt affinity.
  *
  * Due to this model, all interrupts need to be mask/unmasked at two
  * different levels: at the global level and at the per-CPU level.
@@ -91,9 +90,8 @@
  *    the current CPU, running the ->map() code. This allows to have
  *    the interrupt unmasked at this level in non-SMP
  *    configurations. In SMP configurations, the ->set_affinity()
- *    callback is called, which using the
- *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
- *    for the interrupt.
+ *    callback is called, which using the MPIC_INT_SOURCE_CTL()
+ *    readjusts the per-CPU mask/unmask for the interrupt.
  *
  *    The ->mask() and ->unmask() operations only mask/unmask the
  *    interrupt at the "global" level.
@@ -116,25 +114,25 @@
  */
 
 /* Registers relative to main_int_base */
-#define ARMADA_370_XP_INT_CONTROL		0x00
-#define ARMADA_370_XP_SW_TRIG_INT		0x04
-#define ARMADA_370_XP_INT_SET_ENABLE		0x30
-#define ARMADA_370_XP_INT_CLEAR_ENABLE		0x34
-#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + (irq) * 4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
-#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << (cpuid))
+#define MPIC_INT_CONTROL			0x00
+#define MPIC_SW_TRIG_INT			0x04
+#define MPIC_INT_SET_ENABLE			0x30
+#define MPIC_INT_CLEAR_ENABLE			0x34
+#define MPIC_INT_SOURCE_CTL(irq)		(0x100 + (irq) * 4)
+#define MPIC_INT_SOURCE_CPU_MASK		GENMASK(3, 0)
+#define MPIC_INT_IRQ_FIQ_MASK(cpuid)		((BIT(0) | BIT(8)) << (cpuid))
 
 /* Registers relative to per_cpu_int_base */
-#define ARMADA_370_XP_IN_DRBEL_CAUSE		0x08
-#define ARMADA_370_XP_IN_DRBEL_MASK		0x0c
-#define ARMADA_375_PPI_CAUSE			0x10
-#define ARMADA_370_XP_CPU_INTACK		0x44
-#define ARMADA_370_XP_INT_SET_MASK		0x48
-#define ARMADA_370_XP_INT_CLEAR_MASK		0x4C
-#define ARMADA_370_XP_INT_FABRIC_MASK		0x54
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
+#define MPIC_IN_DRBEL_CAUSE			0x08
+#define MPIC_IN_DRBEL_MASK			0x0c
+#define MPIC_PPI_CAUSE				0x10
+#define MPIC_CPU_INTACK				0x44
+#define MPIC_INT_SET_MASK			0x48
+#define MPIC_INT_CLEAR_MASK			0x4C
+#define MPIC_INT_FABRIC_MASK			0x54
+#define MPIC_INT_CAUSE_PERF(cpu)		BIT(cpu)
 
-#define ARMADA_370_XP_MAX_PER_CPU_IRQS		28
+#define MPIC_MAX_PER_CPU_IRQS			28
 
 /* IPI and MSI interrupt definitions for IPI platforms */
 #define IPI_DOORBELL_START			0
@@ -203,7 +201,7 @@ static inline unsigned int msi_doorbell_end(void)
 
 static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
-	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
+	if (irq <= MPIC_MAX_PER_CPU_IRQS)
 		return true;
 
 	return false;
@@ -219,9 +217,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+		writel(hwirq, main_int_base + MPIC_INT_CLEAR_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+		writel(hwirq, per_cpu_int_base + MPIC_INT_SET_MASK);
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)
@@ -229,9 +227,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
 	if (!is_percpu_irq(hwirq))
-		writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+		writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE);
 	else
-		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 #ifdef CONFIG_PCI_MSI
@@ -324,18 +322,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
 	u32 reg;
 
 	/* Enable MSI doorbell mask and combined cpu local interrupt */
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg |= msi_doorbell_mask();
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	/* Unmask local doorbell interrupt */
-	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+	writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 static int armada_370_xp_msi_init(struct device_node *node,
 				  phys_addr_t main_int_phys_base)
 {
-	msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
+	msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT;
 
 	armada_370_xp_msi_inner_domain =
 		irq_domain_add_linear(NULL, msi_doorbell_size(),
@@ -356,7 +354,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
 
 	/* Unmask low 16 MSI irqs on non-IPI platforms */
 	if (!is_ipi_available())
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
 	return 0;
 }
@@ -384,8 +382,8 @@ static void armada_xp_mpic_perf_init(void)
 	cpuid = cpu_logical_map(smp_processor_id());
 
 	/* Enable Performance Counter Overflow interrupts */
-	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
-	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
+	writel(MPIC_INT_CAUSE_PERF(cpuid),
+	       per_cpu_int_base + MPIC_INT_FABRIC_MASK);
 }
 
 #ifdef CONFIG_SMP
@@ -394,17 +392,17 @@ static struct irq_domain *ipi_domain;
 static void armada_370_xp_ipi_mask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg &= ~BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_unmask(struct irq_data *d)
 {
 	u32 reg;
-	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	reg |= BIT(d->hwirq);
-	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 }
 
 static void armada_370_xp_ipi_send_mask(struct irq_data *d,
@@ -424,13 +422,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 	dsb();
 
 	/* submit softirq */
-	writel((map << 8) | d->hwirq, main_int_base +
-		ARMADA_370_XP_SW_TRIG_INT);
+	writel((map << 8) | d->hwirq, main_int_base + MPIC_SW_TRIG_INT);
 }
 
 static void armada_370_xp_ipi_ack(struct irq_data *d)
 {
-	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(~BIT(d->hwirq), per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 }
 
 static struct irq_chip ipi_irqchip = {
@@ -515,9 +512,8 @@ static int armada_xp_set_affinity(struct irq_data *d,
 	/* Select a single core from the affinity mask which is online */
 	cpu = cpumask_any_and(mask_val, cpu_online_mask);
 
-	atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq),
-			 ARMADA_370_XP_INT_SOURCE_CPU_MASK,
-			 BIT(cpu_logical_map(cpu)));
+	atomic_io_modify(main_int_base + MPIC_INT_SOURCE_CTL(hwirq),
+			 MPIC_INT_SOURCE_CPU_MASK, BIT(cpu_logical_map(cpu)));
 
 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
 
@@ -529,23 +525,23 @@ static void armada_xp_mpic_smp_cpu_init(void)
 	u32 control;
 	int nr_irqs, i;
 
-	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
+		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!is_ipi_available())
 		return;
 
 	/* Disable all IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(0, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	/* Clear pending IPIs */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(0, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 
 	/* Unmask IPI interrupt */
-	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+	writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 }
 
 static void armada_xp_mpic_reenable_percpu(void)
@@ -553,7 +549,7 @@ static void armada_xp_mpic_reenable_percpu(void)
 	unsigned int irq;
 
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
-	for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
+	for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
 		struct irq_data *data;
 		int virq;
 
@@ -615,10 +611,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 
 	armada_370_xp_irq_mask(irq_get_irq_data(virq));
 	if (!is_percpu_irq(hw))
-		writel(hw, per_cpu_int_base +
-			ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	else
-		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
+		writel(hw, main_int_base + MPIC_INT_SET_ENABLE);
 	irq_set_status_flags(virq, IRQ_LEVEL);
 
 	if (is_percpu_irq(hw)) {
@@ -645,10 +640,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
 {
 	u32 msimask, msinr;
 
-	msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	msimask = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 	msimask &= msi_doorbell_mask();
 
-	writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
+	writel(~msimask, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE);
 
 	for (msinr = msi_doorbell_start();
 	     msinr < msi_doorbell_end(); msinr++) {
@@ -673,17 +668,16 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
 
 	chained_irq_enter(chip, desc);
 
-	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
+	irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
 	cpuid = cpu_logical_map(smp_processor_id());
 
 	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
-		irqsrc = readl_relaxed(main_int_base +
-				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));
+		irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn));
 
 		/* Check if the interrupt is not masked on current CPU.
 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
 		 */
-		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
+		if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)))
 			continue;
 
 		if (irqn == 0 || irqn == 1) {
@@ -703,8 +697,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 	u32 irqstat, irqnr;
 
 	do {
-		irqstat = readl_relaxed(per_cpu_int_base +
-					ARMADA_370_XP_CPU_INTACK);
+		irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK);
 		irqnr = irqstat & 0x3FF;
 
 		if (irqnr > 1022)
@@ -727,7 +720,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 			int ipi;
 
 			ipimask = readl_relaxed(per_cpu_int_base +
-						ARMADA_370_XP_IN_DRBEL_CAUSE)
+						MPIC_IN_DRBEL_CAUSE)
 				& IPI_DOORBELL_MASK;
 
 			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
@@ -740,7 +733,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
 
 static int armada_370_xp_mpic_suspend(void)
 {
-	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 	return 0;
 }
 
@@ -751,7 +744,7 @@ static void armada_370_xp_mpic_resume(void)
 	irq_hw_number_t irq;
 
 	/* Re-enable interrupts */
-	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
+	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
 	for (irq = 0; irq < nirqs; irq++) {
 		struct irq_data *data;
 		int virq;
@@ -764,14 +757,12 @@ static void armada_370_xp_mpic_resume(void)
 
 		if (!is_percpu_irq(irq)) {
 			/* Non per-CPU interrupts */
-			writel(irq, per_cpu_int_base +
-			       ARMADA_370_XP_INT_CLEAR_MASK);
+			writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 			if (!irqd_irq_disabled(data))
 				armada_370_xp_irq_unmask(data);
 		} else {
 			/* Per-CPU interrupts */
-			writel(irq, main_int_base +
-			       ARMADA_370_XP_INT_SET_ENABLE);
+			writel(irq, main_int_base + MPIC_INT_SET_ENABLE);
 
 			/*
 			 * Re-enable on the current CPU,
@@ -784,8 +775,7 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	/* Reconfigure doorbells for IPIs and MSIs */
-	writel(doorbell_mask_reg,
-	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
+	writel(doorbell_mask_reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK);
 
 	if (is_ipi_available()) {
 		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
@@ -796,9 +786,9 @@ static void armada_370_xp_mpic_resume(void)
 	}
 
 	if (src0)
-		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 	if (src1)
-		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
+		writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK);
 
 	if (is_ipi_available())
 		ipi_resume();
@@ -834,11 +824,11 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 				   resource_size(&per_cpu_int_res));
 	BUG_ON(!per_cpu_int_base);
 
-	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
 	for (i = 0; i < nr_irqs; i++)
-		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
+		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =
 		irq_domain_add_linear(node, nr_irqs,
-- 
2.44.2

[PATCH v3 07/10] irqchip/armada-370-xp: Use correct type for cpu variable

[Marek Behún]

Use unsigned int instead of int for variable storing the cpu number.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 8f52de6d8921..b9631cc25c0b 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -409,7 +409,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 					const struct cpumask *mask)
 {
 	unsigned long map = 0;
-	int cpu;
+	unsigned int cpu;
 
 	/* Convert our logical CPU mask into a physical one. */
 	for_each_cpu(cpu, mask)
@@ -507,7 +507,7 @@ static int armada_xp_set_affinity(struct irq_data *d,
 				  const struct cpumask *mask_val, bool force)
 {
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
-	int cpu;
+	unsigned int cpu;
 
 	/* Select a single core from the affinity mask which is online */
 	cpu = cpumask_any_and(mask_val, cpu_online_mask);
-- 
2.44.2

[PATCH v3 08/10] irqchip/armada-370-xp: Simplify is_percpu_irq() code

[Marek Behún]

Simplify the code in the is_percpu_irq() function. Instead of
  if (condition)
    return true;
  return false;
simply return condition.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 drivers/irqchip/irq-armada-370-xp.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index b9631cc25c0b..cfd6dc803150 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -201,10 +201,7 @@ static inline unsigned int msi_doorbell_end(void)
 
 static inline bool is_percpu_irq(irq_hw_number_t irq)
 {
-	if (irq <= MPIC_MAX_PER_CPU_IRQS)
-		return true;
-
-	return false;
+	return irq <= MPIC_MAX_PER_CPU_IRQS;
 }
 
 /*
-- 
2.44.2

[PATCH v3 09/10] irqchip/armada-370-xp: Change to SPDX license identifier

[Marek Behún]

Change the license identifier to SPDX style.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index cfd6dc803150..3d15d0bb7605 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Armada 370 and Armada XP SoC IRQ handling
  *
@@ -7,10 +8,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Ben Dooks <ben.dooks@codethink.co.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/bits.h>
-- 
2.44.2

[PATCH v3 10/10] irqchip/armada-370-xp: Declare iterators in for loop

[Marek Behún]

Where possible, declare iterators in for cycle. This is possible since
kernel uses -std=gnu11.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/irqchip/irq-armada-370-xp.c | 27 ++++++++++-----------------
 1 file changed, 10 insertions(+), 17 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 3d15d0bb7605..22e1a493abae 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -276,7 +276,7 @@ static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
 static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 				   unsigned int nr_irqs, void *args)
 {
-	int hwirq, i;
+	int hwirq;
 
 	mutex_lock(&msi_used_lock);
 	hwirq = bitmap_find_free_region(msi_used, msi_doorbell_size(),
@@ -286,7 +286,7 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
 	if (hwirq < 0)
 		return -ENOSPC;
 
-	for (i = 0; i < nr_irqs; i++) {
+	for (int i = 0; i < nr_irqs; i++) {
 		irq_domain_set_info(domain, virq + i, hwirq + i,
 				    &armada_370_xp_msi_bottom_irq_chip,
 				    domain->host_data, handle_simple_irq,
@@ -436,9 +436,7 @@ static int armada_370_xp_ipi_alloc(struct irq_domain *d,
 					 unsigned int virq,
 					 unsigned int nr_irqs, void *args)
 {
-	int i;
-
-	for (i = 0; i < nr_irqs; i++) {
+	for (int i = 0; i < nr_irqs; i++) {
 		irq_set_percpu_devid(virq + i);
 		irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
 				    d->host_data,
@@ -463,9 +461,7 @@ static const struct irq_domain_ops ipi_domain_ops = {
 
 static void ipi_resume(void)
 {
-	int i;
-
-	for (i = 0; i < IPI_DOORBELL_END; i++) {
+	for (int i = 0; i < IPI_DOORBELL_END; i++) {
 		int irq;
 
 		irq = irq_find_mapping(ipi_domain, i);
@@ -517,12 +513,12 @@ static int armada_xp_set_affinity(struct irq_data *d,
 static void armada_xp_mpic_smp_cpu_init(void)
 {
 	u32 control;
-	int nr_irqs, i;
+	int nr_irqs;
 
 	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
-	for (i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < nr_irqs; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!is_ipi_available())
@@ -540,10 +536,8 @@ static void armada_xp_mpic_smp_cpu_init(void)
 
 static void armada_xp_mpic_reenable_percpu(void)
 {
-	unsigned int irq;
-
 	/* Re-enable per-CPU interrupts that were enabled before suspend */
-	for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
+	for (unsigned int irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) {
 		struct irq_data *data;
 		int virq;
 
@@ -735,11 +729,10 @@ static void armada_370_xp_mpic_resume(void)
 {
 	bool src0, src1;
 	int nirqs;
-	irq_hw_number_t irq;
 
 	/* Re-enable interrupts */
 	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
-	for (irq = 0; irq < nirqs; irq++) {
+	for (irq_hw_number_t irq = 0; irq < nirqs; irq++) {
 		struct irq_data *data;
 		int virq;
 
@@ -797,7 +790,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 					     struct device_node *parent)
 {
 	struct resource main_int_res, per_cpu_int_res;
-	int nr_irqs, i;
+	int nr_irqs;
 	u32 control;
 
 	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
@@ -821,7 +814,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 	control = readl(main_int_base + MPIC_INT_CONTROL);
 	nr_irqs = (control >> 2) & 0x3ff;
 
-	for (i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < nr_irqs; i++)
 		writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE);
 
 	armada_370_xp_mpic_domain =
-- 
2.44.2

Re: [PATCH v3 02/10] irqchip/armada-370-xp: Change register constant suffix from _MSK to _MASK

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 3545 bytes --]

On Mon, 8 Jul 2024, Marek Behún wrote:

> There is one occurrence of suffix _MSK in register constants, others
> have _MASK instead. Change the one to _MASK for consistency.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> ---
>  drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index 66d6a2ebc8a5..588a9e2e1887 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -126,7 +126,7 @@
>  
>  /* Registers relative to per_cpu_int_base */
>  #define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
> -#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
> +#define ARMADA_370_XP_IN_DRBEL_MASK		(0x0c)
>  #define ARMADA_375_PPI_CAUSE			(0x10)
>  #define ARMADA_370_XP_CPU_INTACK		(0x44)
>  #define ARMADA_370_XP_INT_SET_MASK		(0x48)
> @@ -324,9 +324,9 @@ static void armada_370_xp_msi_reenable_percpu(void)
>  	u32 reg;
>  
>  	/* Enable MSI doorbell mask and combined cpu local interrupt */
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  	reg |= msi_doorbell_mask();
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  
>  	/* Unmask local doorbell interrupt */
>  	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
> @@ -394,17 +394,17 @@ static struct irq_domain *ipi_domain;
>  static void armada_370_xp_ipi_mask(struct irq_data *d)
>  {
>  	u32 reg;
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  	reg &= ~BIT(d->hwirq);
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  }
>  
>  static void armada_370_xp_ipi_unmask(struct irq_data *d)
>  {
>  	u32 reg;
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  	reg |= BIT(d->hwirq);
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  }
>  
>  static void armada_370_xp_ipi_send_mask(struct irq_data *d,
> @@ -539,7 +539,7 @@ static void armada_xp_mpic_smp_cpu_init(void)
>  		return;
>  
>  	/* Disable all IPIs */
> -	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  
>  	/* Clear pending IPIs */
>  	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
> @@ -740,7 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
>  
>  static int armada_370_xp_mpic_suspend(void)
>  {
> -	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  	return 0;
>  }
>  
> @@ -785,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
>  
>  	/* Reconfigure doorbells for IPIs and MSIs */
>  	writel(doorbell_mask_reg,
> -	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
> +	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK);
>  
>  	if (is_ipi_available()) {
>  		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
> 

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

Re: [PATCH v3 03/10] irqchip/armada-370-xp: Change spaces to tabs

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 1554 bytes --]

On Mon, 8 Jul 2024, Marek Behún wrote:

> Change spaces to tabs in register constants definitions.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> ---
>  drivers/irqchip/irq-armada-370-xp.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index 588a9e2e1887..427ba5fd6adc 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -137,13 +137,13 @@
>  #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
>  
>  /* IPI and MSI interrupt definitions for IPI platforms */
> -#define IPI_DOORBELL_START                      (0)
> -#define IPI_DOORBELL_END                        (8)
> -#define IPI_DOORBELL_MASK                       0xFF
> -#define PCI_MSI_DOORBELL_START                  (16)
> -#define PCI_MSI_DOORBELL_NR                     (16)
> -#define PCI_MSI_DOORBELL_END                    (32)
> -#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000
> +#define IPI_DOORBELL_START			(0)
> +#define IPI_DOORBELL_END			(8)
> +#define IPI_DOORBELL_MASK			0xFF
> +#define PCI_MSI_DOORBELL_START			(16)
> +#define PCI_MSI_DOORBELL_NR			(16)
> +#define PCI_MSI_DOORBELL_END			(32)
> +#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
>  
>  /* MSI interrupt definitions for non-IPI platforms */
>  #define PCI_MSI_FULL_DOORBELL_START		0
> 

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

Re: [PATCH v3 01/10] irqchip/armada-370-xp: Drop _OFFS suffix from some register constants

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 12089 bytes --]

On Mon, 8 Jul 2024, Marek Behún wrote:

> Some register constants have the _OFFS suffix and some do not. Drop it
> to be more consistent.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

> ---
>  drivers/irqchip/irq-armada-370-xp.c | 105 +++++++++++++---------------
>  1 file changed, 48 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index dce2b80bf439..66d6a2ebc8a5 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -66,15 +66,14 @@
>   *                   device
>   *
>   * The "global interrupt mask/unmask" is modified using the
> - * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
> - * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
> - * to "main_int_base".
> + * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE
> + * registers, which are relative to "main_int_base".
>   *
>   * The "per-CPU mask/unmask" is modified using the
> - * ARMADA_370_XP_INT_SET_MASK_OFFS and
> - * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
> - * "per_cpu_int_base". This base address points to a special address,
> - * which automatically accesses the registers of the current CPU.
> + * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK
> + * registers, which are relative to "per_cpu_int_base". This base
> + * address points to a special address, which automatically accesses
> + * the registers of the current CPU.
>   *
>   * The per-CPU mask/unmask can also be adjusted using the global
>   * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
> @@ -118,21 +117,21 @@
>  
>  /* Registers relative to main_int_base */
>  #define ARMADA_370_XP_INT_CONTROL		(0x00)
> -#define ARMADA_370_XP_SW_TRIG_INT_OFFS		(0x04)
> -#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
> -#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
> +#define ARMADA_370_XP_SW_TRIG_INT		(0x04)
> +#define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
> +#define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
>  #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
>  #define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
>  #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
>  
>  /* Registers relative to per_cpu_int_base */
> -#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS	(0x08)
> -#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS		(0x0c)
> +#define ARMADA_370_XP_IN_DRBEL_CAUSE		(0x08)
> +#define ARMADA_370_XP_IN_DRBEL_MSK		(0x0c)
>  #define ARMADA_375_PPI_CAUSE			(0x10)
> -#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
> -#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
> -#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
> -#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
> +#define ARMADA_370_XP_CPU_INTACK		(0x44)
> +#define ARMADA_370_XP_INT_SET_MASK		(0x48)
> +#define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
> +#define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
>  #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
>  
>  #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
> @@ -220,11 +219,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
>  	irq_hw_number_t hwirq = irqd_to_hwirq(d);
>  
>  	if (!is_percpu_irq(hwirq))
> -		writel(hwirq, main_int_base +
> -				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
> +		writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
>  	else
> -		writel(hwirq, per_cpu_int_base +
> -				ARMADA_370_XP_INT_SET_MASK_OFFS);
> +		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
>  }
>  
>  static void armada_370_xp_irq_unmask(struct irq_data *d)
> @@ -232,11 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
>  	irq_hw_number_t hwirq = irqd_to_hwirq(d);
>  
>  	if (!is_percpu_irq(hwirq))
> -		writel(hwirq, main_int_base +
> -				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
> +		writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
>  	else
> -		writel(hwirq, per_cpu_int_base +
> -				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +		writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  }
>  
>  #ifdef CONFIG_PCI_MSI
> @@ -329,19 +324,18 @@ static void armada_370_xp_msi_reenable_percpu(void)
>  	u32 reg;
>  
>  	/* Enable MSI doorbell mask and combined cpu local interrupt */
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  	reg |= msi_doorbell_mask();
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  
>  	/* Unmask local doorbell interrupt */
> -	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  }
>  
>  static int armada_370_xp_msi_init(struct device_node *node,
>  				  phys_addr_t main_int_phys_base)
>  {
> -	msi_doorbell_addr = main_int_phys_base +
> -		ARMADA_370_XP_SW_TRIG_INT_OFFS;
> +	msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT;
>  
>  	armada_370_xp_msi_inner_domain =
>  		irq_domain_add_linear(NULL, msi_doorbell_size(),
> @@ -362,7 +356,7 @@ static int armada_370_xp_msi_init(struct device_node *node,
>  
>  	/* Unmask low 16 MSI irqs on non-IPI platforms */
>  	if (!is_ipi_available())
> -		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  
>  	return 0;
>  }
> @@ -391,7 +385,7 @@ static void armada_xp_mpic_perf_init(void)
>  
>  	/* Enable Performance Counter Overflow interrupts */
>  	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
> -	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
> +	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK);
>  }
>  
>  #ifdef CONFIG_SMP
> @@ -400,17 +394,17 @@ static struct irq_domain *ipi_domain;
>  static void armada_370_xp_ipi_mask(struct irq_data *d)
>  {
>  	u32 reg;
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  	reg &= ~BIT(d->hwirq);
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  }
>  
>  static void armada_370_xp_ipi_unmask(struct irq_data *d)
>  {
>  	u32 reg;
> -	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  	reg |= BIT(d->hwirq);
> -	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  }
>  
>  static void armada_370_xp_ipi_send_mask(struct irq_data *d,
> @@ -431,12 +425,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
>  
>  	/* submit softirq */
>  	writel((map << 8) | d->hwirq, main_int_base +
> -		ARMADA_370_XP_SW_TRIG_INT_OFFS);
> +		ARMADA_370_XP_SW_TRIG_INT);
>  }
>  
>  static void armada_370_xp_ipi_ack(struct irq_data *d)
>  {
> -	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
> +	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
>  }
>  
>  static struct irq_chip ipi_irqchip = {
> @@ -539,19 +533,19 @@ static void armada_xp_mpic_smp_cpu_init(void)
>  	nr_irqs = (control >> 2) & 0x3ff;
>  
>  	for (i = 0; i < nr_irqs; i++)
> -		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
> +		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK);
>  
>  	if (!is_ipi_available())
>  		return;
>  
>  	/* Disable all IPIs */
> -	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  
>  	/* Clear pending IPIs */
> -	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
> +	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
>  
>  	/* Unmask IPI interrupt */
> -	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  }
>  
>  static void armada_xp_mpic_reenable_percpu(void)
> @@ -622,9 +616,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
>  	armada_370_xp_irq_mask(irq_get_irq_data(virq));
>  	if (!is_percpu_irq(hw))
>  		writel(hw, per_cpu_int_base +
> -			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +			ARMADA_370_XP_INT_CLEAR_MASK);
>  	else
> -		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
> +		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE);
>  	irq_set_status_flags(virq, IRQ_LEVEL);
>  
>  	if (is_percpu_irq(hw)) {
> @@ -651,12 +645,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
>  {
>  	u32 msimask, msinr;
>  
> -	msimask = readl_relaxed(per_cpu_int_base +
> -				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
> +	msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
>  	msimask &= msi_doorbell_mask();
>  
> -	writel(~msimask, per_cpu_int_base +
> -	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
> +	writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE);
>  
>  	for (msinr = msi_doorbell_start();
>  	     msinr < msi_doorbell_end(); msinr++) {
> @@ -712,7 +704,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
>  
>  	do {
>  		irqstat = readl_relaxed(per_cpu_int_base +
> -					ARMADA_370_XP_CPU_INTACK_OFFS);
> +					ARMADA_370_XP_CPU_INTACK);
>  		irqnr = irqstat & 0x3FF;
>  
>  		if (irqnr > 1022)
> @@ -735,7 +727,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
>  			int ipi;
>  
>  			ipimask = readl_relaxed(per_cpu_int_base +
> -						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
> +						ARMADA_370_XP_IN_DRBEL_CAUSE)
>  				& IPI_DOORBELL_MASK;
>  
>  			for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
> @@ -748,8 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
>  
>  static int armada_370_xp_mpic_suspend(void)
>  {
> -	doorbell_mask_reg = readl(per_cpu_int_base +
> -				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  	return 0;
>  }
>  
> @@ -774,13 +765,13 @@ static void armada_370_xp_mpic_resume(void)
>  		if (!is_percpu_irq(irq)) {
>  			/* Non per-CPU interrupts */
>  			writel(irq, per_cpu_int_base +
> -			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +			       ARMADA_370_XP_INT_CLEAR_MASK);
>  			if (!irqd_irq_disabled(data))
>  				armada_370_xp_irq_unmask(data);
>  		} else {
>  			/* Per-CPU interrupts */
>  			writel(irq, main_int_base +
> -			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);
> +			       ARMADA_370_XP_INT_SET_ENABLE);
>  
>  			/*
>  			 * Re-enable on the current CPU,
> @@ -794,7 +785,7 @@ static void armada_370_xp_mpic_resume(void)
>  
>  	/* Reconfigure doorbells for IPIs and MSIs */
>  	writel(doorbell_mask_reg,
> -	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
> +	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK);
>  
>  	if (is_ipi_available()) {
>  		src0 = doorbell_mask_reg & IPI_DOORBELL_MASK;
> @@ -805,9 +796,9 @@ static void armada_370_xp_mpic_resume(void)
>  	}
>  
>  	if (src0)
> -		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  	if (src1)
> -		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
> +		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK);
>  
>  	if (is_ipi_available())
>  		ipi_resume();
> @@ -847,7 +838,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
>  	nr_irqs = (control >> 2) & 0x3ff;
>  
>  	for (i = 0; i < nr_irqs; i++)
> -		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
> +		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE);
>  
>  	armada_370_xp_mpic_domain =
>  		irq_domain_add_linear(node, nr_irqs,
> 

Re: [PATCH v3 04/10] irqchip/armada-370-xp: Use BIT() and GENMASK() macros

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 2312 bytes --]

On Mon, 8 Jul 2024, Marek Behún wrote:

> Use the BIT() and GENMASK() macros where appropriate.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>

Are #includes missing for GENMASK() and BIT()? (Or is this based on some 
tree which already has them?)

-- 
 i.

> ---
>  drivers/irqchip/irq-armada-370-xp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
> index 427ba5fd6adc..18aca9b5d3b3 100644
> --- a/drivers/irqchip/irq-armada-370-xp.c
> +++ b/drivers/irqchip/irq-armada-370-xp.c
> @@ -121,7 +121,7 @@
>  #define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
>  #define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
>  #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
> -#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
> +#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
>  #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
>  
>  /* Registers relative to per_cpu_int_base */
> @@ -132,18 +132,18 @@
>  #define ARMADA_370_XP_INT_SET_MASK		(0x48)
>  #define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
>  #define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
> -#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
> +#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
>  
>  #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
>  
>  /* IPI and MSI interrupt definitions for IPI platforms */
>  #define IPI_DOORBELL_START			(0)
>  #define IPI_DOORBELL_END			(8)
> -#define IPI_DOORBELL_MASK			0xFF
> +#define IPI_DOORBELL_MASK			GENMASK(7, 0)
>  #define PCI_MSI_DOORBELL_START			(16)
>  #define PCI_MSI_DOORBELL_NR			(16)
>  #define PCI_MSI_DOORBELL_END			(32)
> -#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
> +#define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
>  
>  /* MSI interrupt definitions for non-IPI platforms */
>  #define PCI_MSI_FULL_DOORBELL_START		0
> @@ -415,7 +415,7 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d,
>  
>  	/* Convert our logical CPU mask into a physical one. */
>  	for_each_cpu(cpu, mask)
> -		map |= 1 << cpu_logical_map(cpu);
> +		map |= BIT(cpu_logical_map(cpu));
>  
>  	/*
>  	 * Ensure that stores to Normal memory are visible to the
> 

Re: [PATCH v3 10/10] irqchip/armada-370-xp: Declare iterators in for loop

[Andrew Lunn]

On Mon, Jul 08, 2024 at 05:18:01PM +0200, Marek Behún wrote:
> Where possible, declare iterators in for cycle. This is possible since
> kernel uses -std=gnu11.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v3 04/10] irqchip/armada-370-xp: Use BIT() and GENMASK() macros

[Marek Behún]

On Mon, 8 Jul 2024 19:27:52 +0300 (EEST)
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:

> On Mon, 8 Jul 2024, Marek Behún wrote:
> 
> > Use the BIT() and GENMASK() macros where appropriate.
> > 
> > Signed-off-by: Marek Behún <kabel@kernel.org>
> > Reviewed-by: Andrew Lunn <andrew@lunn.ch>  
> 
> Are #includes missing for GENMASK() and BIT()? (Or is this based on some 
> tree which already has them?)

#include <linux/bits.h> was added in another patch that was already
accepted to tip.git irq/core branch (and merged into tip.git master
branch):
  https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=986b6ad0c4c653940fab7e5decf0d847670bf407

Marek