From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 541BDC3271E for ; Mon, 8 Jul 2024 15:19:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eNS60y6RDflskwmWnRNwKoL0kqyYpLlEkysuWeyt1mc=; b=lMOZU9ih3S91C40ZvoAx5rI3Pp UFHy7N3q5SaLTG9j6DAXB72knnjgH4Ec/kjW4EYOXyGx3Z7zEdW8Nrqi0Fbk/3Fszrps4Z/r5Ga1I pMGAaFmOgYO1Fn3aLCmvqIFv317+iXSP1Xcqc9BUHzozL2WQ/XVd/DlPCAI/Ms3c2m//AC8RXOEHF Q+WMCDBVThcSifq8wQEUioLla2ZnspNUM2tvOlpI7bos9/NPQoU1ftUj5hbWO9eewdq+We7sK6be3 AeWVOl37yea1Ec3xDhglP6eBmUlvXg/XrXikiTw5DeyLdZBM+MPt3qPsb8wfqbCRx/DBHBedFOlOt UT6jM+ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sQq9I-00000004Bht-2vgN; Mon, 08 Jul 2024 15:19:28 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sQq8D-00000004BLE-0asU for linux-arm-kernel@lists.infradead.org; Mon, 08 Jul 2024 15:18:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id ACAAF60E9F; Mon, 8 Jul 2024 15:18:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D5B7C116B1; Mon, 8 Jul 2024 15:18:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720451900; bh=eMZTgG1nMvUW+eafCcXHanhYAtc/BTEckYwEStfIkFg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NBSFQZPe7cM7qWdDCYsdFEmK9F6qBTS0qPGQLUCvGr0vL9wSF4wsv6ulJKKUl/keS er6E1RiL6qhEGKafc+DZUOPzxenZ80K0qUrlgo9vnrTWI59PbOmfpUXQTNo3eMTnc0 kEdJbtsU9ZB73+5dXWyeNst4dXOLnWziDCHwROd3YlXJELc2y00V5z3S2krY0Ax8Wt qtUjicKESaqdlCdEZEVD/smW4QAf05wRoxghQowatFoTQ7+xr1hljmL543zEPhdPrq E+JDrrIWQAXTJPfgcIktwgae8M0jPHcQyBU8Pf4XL4Q9YSOZs4sh1uJShD38shTiJr KGvoZFrJI2YRA== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH v3 05/10] irqchip/armada-370-xp: Cosmetic fix parentheses in register constant definitions Date: Mon, 8 Jul 2024 17:17:56 +0200 Message-ID: <20240708151801.11592-6-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240708151801.11592-1-kabel@kernel.org> References: <20240708151801.11592-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240708_081821_279583_CDE35936 X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Drop parentheses where not needed and add where makes sense in register constant definitions. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Reviewed-by: Ilpo Järvinen --- drivers/irqchip/irq-armada-370-xp.c | 38 ++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 18aca9b5d3b3..14d213e9b0d2 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -116,33 +116,33 @@ */ /* Registers relative to main_int_base */ -#define ARMADA_370_XP_INT_CONTROL (0x00) -#define ARMADA_370_XP_SW_TRIG_INT (0x04) -#define ARMADA_370_XP_INT_SET_ENABLE (0x30) -#define ARMADA_370_XP_INT_CLEAR_ENABLE (0x34) -#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) +#define ARMADA_370_XP_INT_CONTROL 0x00 +#define ARMADA_370_XP_SW_TRIG_INT 0x04 +#define ARMADA_370_XP_INT_SET_ENABLE 0x30 +#define ARMADA_370_XP_INT_CLEAR_ENABLE 0x34 +#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) #define ARMADA_370_XP_INT_SOURCE_CPU_MASK GENMASK(3, 0) -#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) +#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) /* Registers relative to per_cpu_int_base */ -#define ARMADA_370_XP_IN_DRBEL_CAUSE (0x08) -#define ARMADA_370_XP_IN_DRBEL_MASK (0x0c) -#define ARMADA_375_PPI_CAUSE (0x10) -#define ARMADA_370_XP_CPU_INTACK (0x44) -#define ARMADA_370_XP_INT_SET_MASK (0x48) -#define ARMADA_370_XP_INT_CLEAR_MASK (0x4C) -#define ARMADA_370_XP_INT_FABRIC_MASK (0x54) +#define ARMADA_370_XP_IN_DRBEL_CAUSE 0x08 +#define ARMADA_370_XP_IN_DRBEL_MASK 0x0c +#define ARMADA_375_PPI_CAUSE 0x10 +#define ARMADA_370_XP_CPU_INTACK 0x44 +#define ARMADA_370_XP_INT_SET_MASK 0x48 +#define ARMADA_370_XP_INT_CLEAR_MASK 0x4C +#define ARMADA_370_XP_INT_FABRIC_MASK 0x54 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) BIT(cpu) -#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +#define ARMADA_370_XP_MAX_PER_CPU_IRQS 28 /* IPI and MSI interrupt definitions for IPI platforms */ -#define IPI_DOORBELL_START (0) -#define IPI_DOORBELL_END (8) +#define IPI_DOORBELL_START 0 +#define IPI_DOORBELL_END 8 #define IPI_DOORBELL_MASK GENMASK(7, 0) -#define PCI_MSI_DOORBELL_START (16) -#define PCI_MSI_DOORBELL_NR (16) -#define PCI_MSI_DOORBELL_END (32) +#define PCI_MSI_DOORBELL_START 16 +#define PCI_MSI_DOORBELL_NR 16 +#define PCI_MSI_DOORBELL_END 32 #define PCI_MSI_DOORBELL_MASK GENMASK(31, 16) /* MSI interrupt definitions for non-IPI platforms */ -- 2.44.2