From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15C4EC2BD09 for ; Tue, 9 Jul 2024 11:44:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+vsXc3noaLNmm2NCrnanBmVTotasz4Ck5s+No9i+3rg=; b=UaSdrDyktWPmXgUVciEAIIAKt3 cOfwCxHwmR5H5Kxu08TgQPdFgYStWxSlUY539zHhcOAjrVJCwXrOXI2aC08UbfsHliD69jf/51V3J SWa/cC9oLF+Dct4K+4CSyQsT+1zMr4pOLS4FqEGNovsniw8LdGu8SxVV4jzdspggq9fjSM7/S8H2f vCSTXD5cZF+pLACEQ6RZykjCq/YPAdeDb7x/IQDSAS93zKjhfT1XckkEXVE3pmnGX2peyoDkn5HZE +XGScT5SOg6aL2mUuqU+93FaZtUUUJ7tcuVOW3TX7LRiok2CxR9Vr+t8BfGJpPHevT89qx6mJ/0PH cuAi2qIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sR9GS-000000071u5-2eP9; Tue, 09 Jul 2024 11:44:08 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sR9G6-000000071iq-3GBb for linux-arm-kernel@lists.infradead.org; Tue, 09 Jul 2024 11:43:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 0DD40CE1171; Tue, 9 Jul 2024 11:43:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46B6AC3277B; Tue, 9 Jul 2024 11:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720525424; bh=ZxDFrvOXfuTsNU7JuLaaGFFmPfePvQEPeXe9Hb2BLpw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pfiQXz0HFMM9t00fsyyKZHGaMb0ABmeWo1Y+pnEGEWD6IPKk9GYURbBtRZHZ7iA5Y TFb+w0EeWTqNUX/JtuOKew9N6CWub0ExXvj3k3kAvbgS5E+irplYxueRIjyzWjdX2Q 9NyVdbgodDmzh9uhuBNs7zLEQCZyXR7OXdNBKxtstQXjOMWpE//Zm0DTCQ4LQ21eEO djApqAZFnVdxXz7gS5A4S/qokGiu8LGSiC9rnwIBqt6CWxlEDXu7tMVO2dQeDmFYP1 N9UjuFKHdl4vBUcOR0PdwwKGklSzQeGivvZLza1SesMljrzWi1rYZ5XqYkr7GqW5Q5 HygwMTdFZBGKA== Date: Tue, 9 Jul 2024 12:43:37 +0100 From: Will Deacon To: Steven Price Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, Catalin Marinas , Marc Zyngier , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni Subject: Re: [PATCH v4 06/15] arm64: Make the PHYS_MASK_SHIFT dynamic Message-ID: <20240709114337.GB13242@willie-the-truck> References: <20240701095505.165383-1-steven.price@arm.com> <20240701095505.165383-7-steven.price@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240701095505.165383-7-steven.price@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_044347_248852_AFDF133B X-CRM114-Status: GOOD ( 22.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 01, 2024 at 10:54:56AM +0100, Steven Price wrote: > Make the PHYS_MASK_SHIFT dynamic for Realms. This is only is required > for masking the PFN from a pte entry. For a realm phys_mask_shift is > reduced if the RMM reports a smaller configured size for the guest. > > The realm configuration splits the address space into two with the top > half being memory shared with the host, and the bottom half being > protected memory. We treat the bit which controls this split as an > attribute bit and hence exclude it (and any higher bits) from the mask. > > Co-developed-by: Suzuki K Poulose > Signed-off-by: Suzuki K Poulose > Signed-off-by: Steven Price > > --- > v3: Drop the MAX_PHYS_MASK{,_SHIFT} definitions as they are no longer > needed. > --- > arch/arm64/include/asm/pgtable-hwdef.h | 6 ------ > arch/arm64/include/asm/pgtable.h | 5 +++++ > arch/arm64/kernel/rsi.c | 5 +++++ > 3 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 9943ff0af4c9..2e3af0693bd8 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -203,12 +203,6 @@ > */ > #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) > > -/* > - * Highest possible physical address supported. > - */ > -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) > -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) > - > #define TTBR_CNP_BIT (UL(1) << 0) > > /* > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index f8efbc128446..11d614d83317 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -39,6 +39,11 @@ > #include > #include > > +extern unsigned int phys_mask_shift; > + > +#define PHYS_MASK_SHIFT (phys_mask_shift) > +#define PHYS_MASK ((1UL << PHYS_MASK_SHIFT) - 1) I tried to figure out where this is actually used so I could understand your comment in the commit message: > This is only is required for masking the PFN from a pte entry The closest thing I could find is in arch/arm64/mm/mmap.c, where the mask is used as part of valid_mmap_phys_addr_range() which exists purely to filter accesses to /dev/mem. That's pretty niche, so why not just inline the RSI-specific stuff in there behind a static key instead of changing these definitions? Or did I miss a subtle user somewhere else? Will