From: Andre Przywara <andre.przywara@arm.com>
To: Luca Fancellu <Luca.Fancellu@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Diego Sueiro <Diego.Sueiro@arm.com>,
Mark Rutland <Mark.Rutland@arm.com>
Subject: Re: [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64
Date: Tue, 16 Jul 2024 14:52:09 +0100 [thread overview]
Message-ID: <20240716145209.47b9575a@donnerap.manchester.arm.com> (raw)
In-Reply-To: <54BD3222-95AD-46F5-B9A4-4049EB0FED94@arm.com>
On Tue, 16 Jul 2024 14:33:08 +0100
Luca Fancellu <Luca.Fancellu@arm.com> wrote:
Hi Luca,
> > A patch to a patch is really hard to read, please send a new version with
> > your proposal.
>
> Sure I will.
>
> >>>
> >>
> >> I think you are right, also, reading again the manual we have the HCR_EL2.EnSCXT bit implemented only when
> >> FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented, otherwise it’s res0, so I think I should check:
> >>
> >> 1) FEAT_CSV2_2 which is implemented if ID_AA64PFR0_EL1.CSV2 is 0010 (2)
> >
> > ... or larger than 2, since CSV2_3 includes all functionality of CSV2_2.
> >
> >> 2) FEAT_CSV2_1p2 which is implemented if ID_AA64PFR1_EL1.CSV2_frac is 0010 (2)
> >
> > ... and ID_AA64PFR0_EL1.CSV2 is 0b0001. Also I think CSV2_frac >= 0b0010.
> >
> >> Does it sounds ok for you?
> >
> > Before this gets too complicated, please check two things:
> > 1) HCR_EL2.EnSCXT is RES0 otherwise, which means we can always write this
> > unconditionally, without adverse effects?
>
> Yes, HCR_EL2.EnSCXT is RES0 otherwise, I guess that if we write 1 when it is not implemented, it is ignored? And
> for the cases where it is implemented, then 1 would be the right value.
> Would it be the right approach? I’ve always avoided to write on reserved fields.
Yeah, I agree it leaves some bitter taste, though the definition of RES0
in the glossary seems to suggest it's safe to do.
In this particular case, which is confined to v8-R64, which implements at
least some kind of CSV2, I personally tend to set HCR_EL2.EnSCXT
unconditionally, accompanied by a comment why it is safe to do so.
Cheers,
Andre
> > 2) The Armv8-R64 supplement defines minimum values for PFR0.CSV2, maybe
> > this simplifies some checks?
>
> I checked but it doesn’t simplifies, so I think I should do:
>
> if ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 2) ||
> ((mrs_field(ID_AA64PFR0_EL1, CSV2) >= 1) && (mrs_field(ID_AA64PFR1_EL1, CSV2_frac) >= 2)))
> hcr |= HCR_EL2_ENSCXT_NOTRAP;
>
> Please let me know your preference.
>
> Cheers,
> Luca
>
> >
> > Cheers,
> > Andre
>
next prev parent reply other threads:[~2024-07-16 13:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-06 13:36 [boot-wrapper 0/7] Add Armv8-R AArch64 support Luca Fancellu
2024-06-06 13:36 ` [boot-wrapper 1/7] aarch64: Rename labels and prepare for lower EL booting Luca Fancellu
2024-06-06 15:54 ` Andre Przywara
2024-06-06 13:36 ` [boot-wrapper 2/7] aarch64: Prepare " Luca Fancellu
2024-06-06 16:30 ` Andre Przywara
2024-06-06 13:36 ` [boot-wrapper 3/7] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET Luca Fancellu
2024-06-06 16:39 ` Andre Przywara
2024-06-06 13:36 ` [boot-wrapper 4/7] gic-v3: Prepare for gicv3 with EL2 Luca Fancellu
2024-06-06 17:10 ` Andre Przywara
2024-06-06 13:36 ` [boot-wrapper 5/7] aarch64: Introduce EL2 boot code for Armv8-R AArch64 Luca Fancellu
2024-06-20 17:22 ` Andre Przywara
2024-06-24 12:22 ` Luca Fancellu
2024-07-15 7:17 ` Luca Fancellu
2024-07-15 13:40 ` Andre Przywara
2024-07-16 13:33 ` Luca Fancellu
2024-07-16 13:52 ` Andre Przywara [this message]
2024-06-06 13:36 ` [boot-wrapper 6/7] aarch64: Support PSCI " Luca Fancellu
2024-06-21 11:01 ` Andre Przywara
2024-06-06 13:36 ` [boot-wrapper 7/7] aarch64: Start Xen on Armv8-R at EL2 Luca Fancellu
2024-06-21 10:36 ` Andre Przywara
2024-06-24 13:28 ` Luca Fancellu
2024-07-15 7:16 ` Luca Fancellu
2024-07-15 13:12 ` Andre Przywara
2024-06-06 15:42 ` [boot-wrapper 0/7] Add Armv8-R AArch64 support Luca Fancellu
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